Super Micro Computer Assigned Three Patents

Automatic configuration of network switch in multi-chassis link aggregation group
Super Micro Computer, Inc., San Jose, CA, has been assigned a patent (11,212,179) developed by Jailani, Sahul Hameed Abdul Kader, San Jose, CA, for an “automatic configuration of a network switch in a multi-chassis link aggregation group.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Various embodiments set forth a method for automatically configuring a multi-chassis link aggregation group, MLAG, including receiving first system information associated with the MLAG, receiving a first discovery packet via a first uplink port associated with a first switch that is included in the MLAG, where the first discovery packet includes second system information associated with the MLAG, determining whether the first system information matches the second system information, where if the first system information matches the second system information, then concluding that the first uplink port is included in an inter peer link connecting the first switch to a second switch that also is included in the MLAG, and if the first system information does not match the second system information, then concluding that the first uplink port is not included in the inter peer link. Advantageously, the method avoids requiring a user to enter hundreds of commands manually.”

The patent application was filed on October 22, 2019 (16/660,721).

Allocating data segments in storage regions of group of storage units
Super Micro Computer, Inc., San Jose, CA, has been assigned a patent (11,209,990) developed by Chien, Hung-Ming, Hsinchu County, Taiwan, for “apparatus and method of allocating data segments in storage regions of group of storage units.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An apparatus including a control unit, a memory having computer program code, and N groups of storage units electrically connected to the control unit is disclosed. Each of the N groups of storage units has N storage units, each of the N storage units has N storage regions, wherein N is a positive integer. The memory and the computer program code configured to, with the control unit, cause the apparatus to perform: storing a first data segment into an i.sup.th storage region of a first storage unit of a k.sup.th group of storage units, storing a fourth data segment into an i.sup.th storage region of a first storage it of a (k+1).sup.th group of storage units, storing a fifth data segment into an i.sup.th storage region of a second storage unit of the (k+1).sup.th group of storage units, and storing a sixth data segment into an i.sup.th storage region of a third storage unit of the, k+1).sup.th group of storage units. Wherein the first data segment is associated with the fourth data segment, the first data segment is independent of the fifth data segment, and the first data segment is independent of the sixth data segment.”

The patent application was filed on March 15, 2019 (16/354,803).

Server chassis
Super Micro Computer, Inc., San Jose, CA, has been assigned a patent (11,197,389) developed by Lin, Ken-Sheng, San Jose, CA, for a “server chassis.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A server chassis includes an outer case including a plurality of outer shells and an insertion space. The outer shell has an inner wall, and an outer rail structure is disposed on the inner wall of the outer shell. The outer rail structures including an outer rail-plate, an outer-rail and a set of ball slide rail. A chassis body is slidably coupled to the insertion space. The chassis body includes inner shells and an accommodating space. An inner rail structure includes an inner rail-plate, and the chassis body is capable of sliding with respect to the outer case through the inner rail-plate inserted in the outer-rail.”

The patent application was filed on April 6, 2020 (16/841,449).