Western Digital Technologies Assigned Twenty Patents

Dynamic memory controller and method for use therewith
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11,150,842) developed by Bommana, Sesibhushana Rao, Telangana, India, and Panda, Mukesh, Odisha, India, for “dynamic memory controller and method for use therewith.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A dynamic memory controller and method for use therewith are provided. In one example, a memory controller comprises dynamically-programmable components that can be used to configure the memory controller to be used with any number of selected host and/or memory types, as well as to enable the memory controller with different error detection/correction functionality.”

The patent application was filed on April 20, 2020 (16/853,233).

NAND dropped command detection and recovery
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11,150,841) developed by Ellis, Robert, Phoenix, AZ, O’Toole, Kevin, Chandler, AZ, and Schmier, Jacob, Gilbert, AZ, for “NAND dropped command detection and recovery.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Aspects of a storage device including a memory and a controller are provided which allow for detection of dropped commands based on a die status (ready/busy status) of a command received from a host device. The memory may include dies controlled by chip-enables (CE). After selecting a die using CE, the controller waits between a minimum and maximum time after receiving the command to query the die status, where the minimum time is the time by which the command is expected to begin execution and the maximum time is the shortest time by which the command is expected to complete execution. The controller queries the die status after waiting the time period. If the die status is ready when it should have read busy, the controller detects that the command associated with the data is dropped and requests the host device to reissue the command.”

The patent application was filed on February 10, 2020 (16/786,889).

Host and method for interleaving data in storage for enhanced quality of service
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11,150,839) developed by Muthiah, Ramanathan, Bangalore, India, for “host and method for interleaving data in a storage system for enhanced quality of service.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A host and method for interleaving data in a storage system for enhanced quality of service are provided. In one embodiment, a host is provided comprising an interface configured to communicate with a storage system comprising a memory. The processor is configured to determine a skip length for interleaving data to be stored in the storage system, interleave data according to the determined skip length, and send the interleaved data to the storage system for storage. Other embodiments are provided.”

The patent application was filed on December 19, 2019 (16/720,455).

Storage and storing scalable video
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11,140,445) developed by Muthiah, Ramanathan, Bangalore, India, for “storage system and method for storing scalable video.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A storage system and method for storing scalable video are provided. In one embodiment, a storage system is presented comprising a memory and a controller. The controller is configured to receive, from a host, video data and a plurality of profiles for the video data, receive, from the host, usage information on each of the plurality of profiles, and store the plurality of profiles in the memory, wherein a profile that is used more frequently is stored in a higher endurance and/or high protection portion of the memory than a profile that is used less frequently. Other embodiments are provided.”

The patent application was filed on June 3, 2020 (16/891,802).

On-chip parity buffer management for storage block combining in non-volatile memory
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11,138,071) developed by Agarwal, Dinesh Kumar, and Sharma, Amit, Bangalore, India, for an “on-chip parity buffer management for storage block combining in non-volatile memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “On-chip XOR parity data management combines storage blocks in non-volatile memory. Multiple source storage blocks are selected to be combined and stored into a destination storage block. Each source storage block includes a data section and a parity section. The parity section includes XOR parity data that enables data recovery of physical pages of the source storage block. The source storage blocks are merged into the destination storage block, which is configured to store multiple bits per memory cell. Parity sections of one or more of the plurality of source storage blocks remain unchanged after merging into the destination storage block.”

The patent application was filed on June 22, 2020 (16/908,147).

Storage and for fast low-density parity check (LDPC) encoding
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11,138,065) developed by Zamir, Ran, Ramat Gan, Israel, Bazarsky, Alexander, Holon, Israel, and Sharon, Eran, Rishon Lezion, Israel, for “storage system and method for fast low-density parity check (LDPC) encoding.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A storage system has a controller with an encoder. The encoder is configured to perform first and second stages of an encoding process in parallel on pipelined data blocks. In this way, while the first stage of the encoding process is being performed on a first data block, the second stage of the encoding process is performed on a second data block.”

The patent application was filed on May 20, 2020 (16/878,910).

Non-volatile storage with hybrid command
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11,137,914) developed by Sela, Rotem, and Tzori, Yiftach, Hod Hasharon, Israel, for a “non-volatile storage system with hybrid command.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A hybrid command is proposed for interacting with a non-volatile memory device. The hybrid command enables a host connected to the non-volatile memory device to both send and receive data using a single command, which removes the need to use separate commands for sending and receiving. Using the one command rather than separate commands increases system performance.”

The patent application was filed on May 7, 2019 (16/405,818).

Instant and permanent self-destruction in 3D NAND for data security purpose
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11,133,074) developed by Li, Liang, Wang, Weihao, Liu, Xiaohua, Shanghai, China, and Reed, David Joaquin, Penang, MY, for “instant and permanent self-destruction method in 3D NAND for data security purpose.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Apparatuses and techniques are described for performing an operation which irreversibly prevents access to a set of memory cells. The operation provides a strong erase bias for select gate transistors of NAND strings. The erase bias induces a phenomenon in the select gate transistors which permanently increases their threshold voltages. This prevents access to the memory cells such as for program or read operations. The operation can involve one or more erase-verify iterations. In each erase-verify iteration, an erase bias is applied to the select gate transistors such as by charging up the channels of the NAND strings and holding a control gate voltage of the select gate transistors at a relatively low level, thereby causing a relatively high channel-to-control gate voltage.”

The patent application was filed on August 4, 2020 (16/984,478).

Non-volatile memory die with deep learning neural network
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11,133,059) developed by Rom, Rami, Zichron-Yacov, Israel, Pele, Ofir, Hod Hasharon, Israel, Bazarsky, Alexander, Holon, Israel, Eliash, Tomer Tzvi, Kfar Saba, Israel, Zamir, Ran, Ramat Gan, Israel, and Inbar, Karin, Ramat-Hasharon, Israel, for a “non-volatile memory die with deep learning neural network.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Exemplary methods and apparatus are provided for implementing a deep learning accelerator (DLA) or other neural network components within the die of a non-volatile memory (NVM) apparatus using, for example, under-the-array circuit components within the die. Some aspects disclosed herein relate to configuring the under-the-array components to implement feedforward DLA operations. Other aspects relate to backpropagation operations. Still other aspects relate to using an NAND-based on-chip copy with update function to facilitate updating synaptic weights of a neural network stored on a die. Other aspects disclosed herein relate to configuring a solid state device (SSD) controller for use with the NVM. In some aspects, the SSD controller includes flash translation layer (FTL) tables configured specifically for use with neural network data stored in the NVM.”

The patent application was filed on December 6, 2018 (16/212,596).

RAID storage with logical data group rebuild
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11,132,256) developed by Roberts, Adam, Moncure, NC, for a “RAID storage system with logical data group rebuild.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Example redundant array of independent disks (RAID) storage systems and methods provide rebuild of logical data groups. Storage devices are configured as a storage array for storing logical data groups distributed among the storage devices. The logical data groups are written in a configuration of RAID stripes in the storage devices. A failed storage device may be rebuilt using the RAID stripes and completed rebuilds of logical blocks may be tracked during the device rebuild process. A logical group rebuild status may be determined by comparing the completed rebuilds of logical blocks to a logical group map. The logical group rebuild status for each logical data group may be provided as complete in response to all logical blocks in the logical data group having been rebuilt. In the event the array rebuild fails, the logical groups that did complete rebuild may be brought online as a partially completed rebuild to prevent the loss of the entire array.”

The patent application was filed on August 3, 2018 (16/054,217).

Implementing redundancy in memory controllers
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11,132,255) developed by Singhai, Ashish, Narasimha, Ashwin, Los Altos, CA, and Okin, Kenneth Alan, San Jose, CA, for “methods and systems for implementing redundancy in memory controllers.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present disclosure relates to methods and systems for implementing redundancy in memory controllers. The disclosed systems and methods utilize a row of memory blocks, such that each memory block in the row is associated with an independent media unit. Failures of the media units are not correlated, and therefore, a failure in one unit does not affect the data stored in the other units. Parity information associated with the data stored in the memory blocks is stored in a separate memory block. If the data in a single memory block has been corrupted, the data stored in the remaining memory blocks and the parity information is used to retrieve the corrupted data.”

The patent application was filed on March 13, 2020 (16/818,949).

Hybrid erase mode for high data retention in memory
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11,127,467) developed by Wang, Ming, Li, Liang, Shanghai, China, and Wan, Jun, San Jose, CA, for a “hybrid erase mode for high data retention in memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Apparatuses and techniques are described for performing an erase operation for a set of memory cells, where the erase operation includes an all word line erase phase to save time followed by an odd-even word line erase phase to improve data retention. A transition to the odd-even word line erase phase can be triggered when the memory cells pass a first verify test which indicates that the threshold voltages of the memory cells have decreased below a first voltage. Or, the transition can be triggered when a threshold number of erase-verify iterations have been performed. The erase operation may be completed when the memory cells pass a second verify test which indicates that the threshold voltages of the memory cells have decreased below a second voltage which is less than the first voltage.”

The patent application was filed on June 19, 2020 (16/906,497).

Magnetic read sensors and related methods having rear hard bias and no AFM layer
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11,127,422) developed by Liu, Xiaoyong, San Jose, CA, Li, Ji, Shenzhen, China, Shang, Changhe, Fremont, CA, Mauri, Daniele, San Jose, CA, and Okada, Yukimasa, Cupertino, CA, for “magnetic read sensors and related methods having a rear hard bias and no AFM layer.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Aspects of the present disclosure generally relate to magnetic recording heads of magnetic recording devices. A magnetic read head includes a first pinning layer magnetically oriented in a first direction, and a second pinning layer formed above the first pinning layer and magnetically oriented in a second direction that is opposite of the first direction. The magnetic read head includes a rear hard bias disposed outwardly of one or more of the first pinning layer relative or the second pinning layer. The rear hard bias is magnetically oriented to generate a magnetic field in a bias direction. The bias direction points in the same direction as the first direction or the second direction. The magnetic read head does not include an antiferromagnetic (AFM) layer between a lower shield and an upper shield.”

The patent application was filed on July 1, 2020 (16/918,848).

HAMR write head with improved corrosion resistance and method for making head
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11,127,421) developed by Siangchaew, Krisda, Nonthaburi, Thailand, Stipe, Barry Cushing, San Jose, CA, and Khamnualthong, Nattaporn, Nonthaburi, Thailand, for “heat-assisted magnetic recording (HAMR) write head with improved corrosion resistance and method for making the head.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A heat-assisted magnetic recording (HAMR) write head has a write pole with a chemically-passivated end that substantially prevents oxidation and thus improves corrosion resistance of the write pole. The write pole and near-field transducer (NFT) are supported on a slider and have their ends in a window region of the slider’s disk-facing surface. The outer surface region of the write pole is chemically-passivated, preferably by exposure to a nitrogen plasma. The nitrogen plasma has no effect on the NFT end or on the magnetoresistive read head, which is protected because it is located in a non-window region of the slider’s disk-facing surface. An optically transparent protective film is formed in the window over the passivated write pole end and NFT end.”

The patent application was filed on February 8, 2021 (17/170,435).

Seed layer for spin torque oscillator in microwave assisted magnetic recording device
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11,127,420) developed by Freitag, James Mac, Sunnyvale, CA, Gao, Zheng, San Jose, CA, Okamura, Susumu, Fujisawa, Japan, and York, Brian, San Jose, CA, for a “seed layer for spin torque oscillator in microwave assisted magnetic recording device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Certain embodiments are directed to a spin torque oscillator (STO) device in a microwave assisted magnetic recording (MAMR) device. The magnetic recording head includes a seed layer, a spin polarization layer over the seed layer, a spacer layer over the spin polarization layer, and a field generation layer is over the spacer layer. In one embodiment, the seed layer comprises a tantalum alloy layer. In another embodiment, the seed layer comprises a template layer and a damping reduction layer over the template layer. In yet another embodiment, the seed layer comprises a texture reset layer, a template layer on the texture reset layer, and a damping reduction layer on the template layer.”

The patent application was filed on June 24, 2019 (16/450,857).

Dual writer for advanced magnetic recording
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11,127,417) developed by Nguyen, Thao A., San Jose, CA, Ho, Michael Kuok San, Emerald Hills, CA, Bai, Zhigang, Fremont, CA, Li, Zhanjie, Pleasanton, CA, and Le, Quang, San Jose, CA, for a “dual writer for advanced magnetic recording.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present disclosure generally relates to a magnetic media drive employing a magnetic recording head. The magnetic recording head comprises a first write head, a second write head, at least one read head, and a thermal fly height control element. The first write head is a wide writing write head comprising a first main pole and a first trailing shield. The second write head a narrow writing write head comprising a second main pole, a trailing gap, a second trailing shield, and one or more side shields. The first main pole has a shorter height and a greater width than the second main pole. The second main pole has a curved or U-shaped surface disposed adjacent to the trailing gap. The thermal fly height control element and the at least one read head are aligned with a center axis of the second main pole of the second write head.”

The patent application was filed on August 24, 2020 (17/001,593).

Privileged execution support for file system commands on storage
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11,126,756) developed by Sadry, Nauzad, Irvine, CA, for “methods and systems for privileged execution support for file system commands on a storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present invention relates to a storage device that is able to execute higher level commands, such as network-level, file-system commands, with privileged access to various resources, such as the storage media, hardware, memory, firmware, etc. In one embodiment, the storage device is configured to receive and execute network-level file-system commands, such as Server-Message-Block protocol commands. In particular, the storage device comprises a drive having a storage media and a communications interface, such as a network interface, and a controller. The controller is configured to interpret and execute network-level, file-system commands received from the communications interface on data stored on the storage media. Accordingly, the storage device can service the network-level, file-system commands more efficiently and without the need for user-space applications.”

The patent application was filed on September 10, 2018 (16/126,579).

Trie search engine
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11,126,624) developed by Brief, David, Modiin, Israel, and Arad, Eran, Misgav, Israel, for a “trie search engine.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method of searching a database that includes executing a trie search algorithm on a first portion of data in the database, returning a tag narrowing a location of the first portion of data to optimize the database, and performing a directed search of the optimized database by executing the trie search algorithm again on the optimized database, where the trie search algorithm is an information retrieval data structure using a M-ary tree where each node consists of a M-positional vector of pointers.”

The patent application was filed on June 11, 2018 (16/004,782).

Storage with improved interface transmitter training
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11,126,585) developed by Joyce, Brian, and Roeser, Mackenzie, Rochester, MN, for a “data storage device with improved interface transmitter training.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present disclosure generally relates to an interface transmitting training method and algorithm. The receiving device can train the transmitting device to choose the correct tap for transmitting from the transmitting device. During the training, the receiving device will send a request for a directional change tap. The transmitting device will note the request, but not act on the request. The receiving device will then send another request for a direction change tap. If the new request is for the same directional change tap as the previous request, and the number of consecutive identical directional change tap requests exceeds a predetermined threshold, the request is executed. By so doing, the effect of randomness for choosing the correct tap is minimized and the link is not degraded by transmitter training. As such, there is an overall improvement in the bit error rate and reliability of the serial interface.”

The patent application was filed on March 9, 2020 (16/812,549).

Storage with improved suspend resume performance
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11,126,369) developed by Ben-Rubi, Refael, Rosh Haayin, Israel, for a “data storage with improved suspend resume performance.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present disclosure generally relates to efficiently reading data during a suspend resume operation. Once writing is suspended, and prior to reading the data, a determination is made regarding whether there are multiple reads of the same page type. If there are multiple reads of the same page type, those reads are paired up so that the two reads of the same page type can occur from two planes in parallel. If two different pages types are read in parallel on the two planes, the slowest page type will determine the duration of the read. By grouping reads of the same page type and proceeding with the read, the disruption during suspend resume operations is minimized.”

The patent application was filed on February 28, 2020 (16/805,570).