IMEC Assigned Two Patents

Memory based on ferroelectric field effect transistors
IMEC vzw, Leuven, Belgium, has been assigned a patent (11,211,404) developed by Salahuddin, Shairfe Muhammad, Leuven, Belgium, Van Houdt, Jan, Bekkevoort, Belgium, Ryckaert, Julien, Schaerbeek, Belgium, and Spessot, Alessio, Heverlee, Belgium, for “memory devices based on ferroelectric field effect transistors.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The disclosed technology is generally directed to semiconductor integrated circuit devices and more particularly to a three-transistor random access memory (3T RAM) device, and a method of fabricating and operating the same. In one aspect, a 3T RAM cell includes a ferroelectric-based field effect transistor (FeFET) having a first gate connected as a storage node and a second transistor connected between the FeFET and a read bit line having a second gate connected to a read word line. The 3T RAM cell also includes a third transistor connected between the storage node and a write bit line having a third gate connected to a write word line.”

The patent application was filed on September 9, 2019 (16/565,112).

Ferroelectric memory
IMEC vzw, Leuven, Belgium, has been assigned a patent (11,211,108) developed by Van Houdt, Jan, Bekkevoort, Belgium , for a “ferroelectric memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The disclosed technology generally relates to a memory device, and more particularly to a ferroelectric memory device and a method of operating the memory device. According to one aspect, a memory device comprises a bit cell. The bit cell comprises a write transistor, a read transistor and a ferroelectric capacitor. A write word line is connected to a gate terminal of the write transistor. A write bit line is connected to a first terminal of the write transistor. A read bit line connected to a terminal of the read transistor. A first control line is connected to a first electrode of the ferroelectric capacitor. A second terminal of the write transistor is connected to the gate terminal of the read transistor, and a second electrode of the ferroelectric capacitor is connected to the second terminal.”

The patent application was filed on December 19, 2018 (16/226,356).