FlashSilicon Assigned Two Patents

Erasing semiconductor non-volatile memories
FlashSilicon Inc., Diamond Bar, CA, has been assigned a patent (11,201,162) developed by Wang, Lee, Diamond Bar, CA, for “methods of erasing semiconductor non-volatile memories.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “For erasing four-terminal semiconductor Non-Volatile Memory (NVM) devices, we apply a high positive voltage bias to the control gate with source, substrate and drain electrodes tied to the ground voltage for moving out stored charges in the charge storage material to the control gate. For improving erasing efficiency and NVM device endurance life by lowering applied voltage biases and reducing the applied voltage time durations, we engineer the lateral impurity profile of the control gate near dielectric interface such that tunneling occurs on the small lateral region of the control gate near the dielectric interface. We also apply the non-uniform thickness of coupling dielectric between the control gate and the storage material for the NVM device such that the tunneling for the erase operation occurs within the small thin dielectric areas, where the electrical field in thin dielectric is the strongest for tunneling erase operation.”

The patent application was filed on December 21, 2018 (16/230,048).

Extendable multiple-digit base-2.sup.n in-memory adder device
FlashSilicon Inc., Diamond Bar, CA, has been assigned a patent (11,200,029) developed by Wang, Lee, Diamond Bar, CA, for an “extendable multiple-digit base-2.sup.n in-memory adder device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The base-2.sup.n in-memory adder device mainly comprises Perpetual Digital Perceptron (PDP) in-memory adder with Read Only Memory (ROM) arrays for storing the binary sum codes of the addition table for processing the addition operations of two n-bit binary integer operands. Since the integer numbers can be represented by the binary codes of multiple digits of base-2.sup.n integer numbers, the base-2.sup.n in-memory adder device can iterate multiple times of the digit-additions to complete the binary code addition for two m-digit base-2.sup.n integer operands. Consequently, the base-2.sup.n in-memory adder device can improve the computation efficiency and save the computation power by eliminating the data transportations between Arithmetic Logic Unit (ALU) registers, and memory units.”

The patent application was filed on April 16, 2020 (16/850,825).