Netlist Assigned Eight Patents

Hybrid memory with configurable error thresholds and failure analysis capability
Netlist, Inc., Irvine, CA, has been assigned a patent (11,200,120) developed by Milton, Scott H., Solomon, Jeffrey C., Irvine, CA, and Post, Kenneth S., Newport Coast, CA, for a “hybrid memory system with configurable error thresholds and failure analysis capability.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A system and method for configuring fault tolerance in nonvolatile memory (NVM) are operative to set a first threshold value, declare one or more portions of NVM invalid based on an error criterion, track the number of declared invalid NVM portions, determine if the tracked number exceeds the first threshold value, and if the tracked number exceeds the first threshold value, perform one or more remediation actions, such as issue a warning or prevent backup of volatile memory data in a hybrid memory system. In the event of backup failure, an extent of the backup can still be assessed by determining the amount of erased NVM that has remained erased after the backup, or by comparing a predicted backup end point with an actual endpoint.”

The patent application was filed on July 19, 2019 (16/517,210).

Memory module having volatile and NVM subsystems and method of operation
Netlist, Inc., Irvine, CA, has been assigned a patent (11,182,284) developed by Lee, Hyun, Ladera Ranch, CA, for “memory module having volatile and non-volatile memory subsystems and method of operation.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory module comprises a volatile memory subsystem, a non-volatile memory subsystem, and a module control device. The module control device is configured to read data from the non-volatile memory subsystem in response to a set of signals received from the memory channel indicating a non-volatile memory access request to transfer the data from the non-volatile memory subsystem to the volatile memory subsystem, and to provide at least a portion of the data to the volatile memory subsystem in response to receiving a dummy write memory command including a memory address related to the non-volatile memory access request via the memory channel. The volatile memory subsystem is further configured to receive the dummy write memory command and to receive the at least a portion of the first data in response to the dummy write memory command.”

The patent application was filed on February 5, 2019 (16/268,454).

Uniform memory access in storage cluster
Netlist, Inc., Irvine, CA, has been assigned a patent (11,176,040) developed by Lee, Hyun, and Ryu, Junkil, Irvine, CA, for “method and apparatus for uniform memory access in a storage cluster.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present application presents a Uniform Memory Access (UMA) network including a cluster of UMA nodes each having at least one UMA memory unit and a server local to the at least one UMA memory unit. A respective UMA memory unit in a respective UMA node comprises persistent memory, non-persistent memory, a node control device operatively coupled to the persistent memory and the non-persistent memory, a local interface for interfacing with the local server in the respective UMA node, and a network interface for interfacing with the UMA network. The node control device is configured to translate between a local unified memory access (UMA) address space accessible by applications running on the local server and a global UMA address space that is mapped to a physical UMA address space. The physical UMA address space includes physical address spaces associated with different UMA nodes in the cluster of UMA nodes. Thus, a server in the UMA network can access the physical address spaces at other UMA nodes without going through the servers in the other UMA nodes.”

The patent application was filed on March 30, 2020 (16/835,024).

Memory module with data buffering
Netlist, Inc., Irvine, CA, has been assigned a patent (11,093,417) developed by Solomon, Jefferey C., Irvine, CA, and Bhakta, Jayesh R., Cerritos, CA, for a “memory module with data buffering.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory module operable to communicate data with a memory controller via a N-bit wide memory bus comprises memory devices arranged in a plurality of N-bit wide ranks. The memory module further comprises logic configurable to receive a set of input address and control signals associated with a read or write memory command and output registered address and control signals and data buffer control signals. The memory module further comprises circuitry coupled between the memory bus and corresponding data pins of memory devices in each of the plurality of N-bit wide ranks. The circuitry is configurable to enable registered transfers of N-bit wide data signals associated with the memory read or write command between the N-bit wide memory bus and the memory devices in response to the data buffer control signals and in accordance with an overall CAS latency of the memory module, which is greater than an actual operational CAS latency of the memory devices.”

The patent application was filed on November 25, 2019 (16/695,020).

Flash-DRAM hybrid memory
Netlist, Inc., Irvine, CA, has been assigned a patent (11,016,918) developed by Chen, Chi-She, Walnut, CA, Solomon, Jeffrey C., Milton, Scott H., Irvine, CA, and Bhakta, Jayesh, Cerritos, CA, for a “flash-DRAM hybrid memory module.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “In certain embodiments, a memory module includes a printed circuit board (PCB) having an interface that couples it to a host system for provision of power, data, address and control signals. First, second, and third buck converters receive a pre-regulated input voltage and produce first, second and third regulated voltages. A converter circuit reduces the pre-regulated input voltage to provide a fourth regulated voltage. Synchronous dynamic random access memory (SDRAM) devices are coupled to one or more regulated voltages of the first, second, third and fourth regulated voltages, and a voltage monitor circuit monitors an input voltage and produces a signal in response to the input voltage having a voltage amplitude that is greater than a threshold voltage.”

The patent application was filed on December 30, 2020 (17/138,766).

Memory module with controlled byte-wise buffers
Netlist, Inc., Irvine, CA, has been assigned a patent (10,949,339) developed by Lee, Hyun, Ladera Ranch, CA, and Bhakta, Jayesh R., Cerritos, CA, for a “memory module with controlled byte-wise buffers.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory module is configured to communicate with a memory controller. The memory module comprises DDR DRAM devices arranged in multiple ranks each of the same width as the memory module, and a module controller configured to receive and register input control signals for a read or write operation from the memory controller and to output registered address and control signals. The registered address and control signals selects one of the multiple ranks to perform the read or write operation. The module controller further outputs a set of module control signals in response to the input address and control signals. The memory module further comprises a plurality of byte-wise buffers controlled by the set of module control signals to actively drive respective byte-wise sections of each data signal associated with the read or write operation between the memory controller and the selected rank.”

The patent application was filed on March 27, 2017 (15/470,856).

Memory module with buffered memory packages
Netlist, Inc., Irvine, CA, has been assigned a patent (10,902,886) developed by Lee, Hyun, Ladera Ranch, CA, for a “memory module with buffered memory packages.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory module includes a plurality of DRAM packages mounted on a printed circuit board. Each DRAM package includes a control die, stacked array dies, and first and second die interconnects coupling the stacked array dies to the control die. The control die includes data signal conduits coupled to the first die interconnects and control signal conduits coupled to the second die interconnects. The control die is configured to receive control signals, and to control the data signal conduits in accordance with the control signals. Each of the DRAM packages is configurable to communicate a respective set of bits of a data signal between a selected die among the stacked array dies and the data conduits in response to the control signals.”

The patent application was filed on May 14, 2019 (16/412,308).

Memory module with local synchronization and method of operation
Netlist, Inc., Irvine, CA, has been assigned a patent (10,884,923) developed by Lee, Hyun, Ladera Ranch, CA, and Bhakta, Jayesh R., Cerritos, CA, for “memory module with local synchronization and method of operation.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory module-includes memory device groups, and a control circuit configurable to receive a system clock and input address and control (C/A) signals from a memory controller, and output a module clock, module C/A signals and data buffer control signals. The memory module further includes data buffers corresponding to respective memory device groups and configurable to receive the module clock and the data buffer control signals from the control circuit. A respective data buffer includes a n-bit wide data path and logic configured to control the data path in response to the data buffer control signals. The n-bit wide data path includes at least one programmable delay element controlled by the logic. The respective data buffer is further configurable to generate a respective local clock having a respective programmable delay from the module clock and to provide the respective local clock to a respective memory device group.”

The patent application was filed on June 5, 2019 (16/432,700).