R&D: Extraction of Nitride Trap Profile in 3D NAND Flash Memory Using Intercell Program Pattern

IEEE Access has published an article written by Jounghun Park, Gilsang Yoon, Donghyun Go, Pohang University of Science and Technology, Pohang, South Korea, Jungsik Kim, Division of Electrical Engineering, Gyeongsang National University, Jinju, South Korea, and Jeong-Soo Lee, Pohang University of Science and Technology, Pohang, South Korea.

Abstract: “The extraction of nitride trap density ( Nt ) filled with electrons emitted by thermal emission (TE) in the charge-trapping layer of 3-D NAND flash memory is demonstrated. The intercell program (IP) pattern was adopted to intentionally inject electrons into the intercell region to minimize the influence of lateral migration (LM) on the trap profiles. This was confirmed by the retention characteristics observed at 120 °C, where the charge loss is mainly caused by the TE of the trapped electrons in the nitride layer. The extracted peak value of Nt at EC – ET value of 1.20 eV using the IP pattern was as low as 1.01×1019 cm ⁻³ eV ⁻¹ , in the scan range of 0.96 eV to 1.27 eV. This value was 17% lower than that from the conventional adjacent cell program (P-P-P) pattern. Therefore, the IP pattern can be used in extracting trap profiles in the SiN layer in scaled 3-D NAND memories.“