Micron Assigned Twenty-Five Patents

Vertical 3D memory and manufacturing
Micron Technology, Inc., Boise, ID, has been assigned a patent (11,158,673) developed by Fantini, Paolo, Vimercate, Italy, Villa, Corrado, Sovico, Italy, and Tessariol, Paolo, Arcore, Italy, for “vertical 3D memory device and method for manufacturing the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A vertical 3D memory device may comprise: a substrate including a plurality of conductive contacts each coupled with a respective one of a plurality of digit lines, a plurality of word line plates separated from one another with respective dielectric layers on the substrate, the plurality of word line plates including at least a first set of word lines separated from at least a second set of word lines with a dielectric material extending in a serpentine shape and at least a third set of word lines separated from at least a fourth set of word lines with a dielectric material extending in a serpentine shape, at least one separation layer separating the first set of word lines and the second set of word lines from the third set of word lines and the fourth set of word lines, wherein the at least one separation layer is parallel to both a digit line and a word line, and a plurality of storage elements each formed in a respective one of a plurality of recesses such that a respective storage element is surrounded by a respective word line, a respective digit line, respective dielectric layers, and a conformal material formed on a sidewall of a word line facing a digit line.”

The patent application was filed on December 18, 2019 (16/771,658).

Namespace management in NVM devices
Micron Technology, Inc., Boise, ID, has been assigned a patent (11,157,173) developed by Frolikov, Alex, San Jose, CA, for “namespace management in non-volatile memory devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A computer storage device having: a host interface, a controller, non-volatile storage media, and firmware. The firmware instructs the controller to: divide a contiguous logical address capacity into blocks according to a predetermined block size, and maintain a data structure to identify: free blocks are available for allocation to new namespaces, and blocks that have been allocated to namespaces in use. Based on the content of the data structure, non-contiguous blocks can be allocated to a namespace, and logical addresses in the namespace can be translated to physical addresses for addressing the non-volatile storage media of the storage device.”

The patent application was filed on August 8, 2019 (16/535,728).

Apparatus comprising monocrystalline semiconductor materials and monocrystalline metal silicide materials
Micron Technology, Inc., Boise, ID, has been assigned a patent (11,152,371) developed by Iwaki, Takayuki, Hiroshima, Japan, for “apparatus comprising monocrystalline semiconductor materials and monocrystalline metal silicide materials, and related methods, electronic devices, and electronic systems.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”An apparatus comprising a memory array comprising wordlines, digit lines, and memory cells, with each memory cell coupled to an associated wordline and an associated digit line. Each memory cell comprises a monocrystalline silicon material adjacent to an access device, a monocrystalline metal silicide material directly contacting the monocrystalline semiconductor material, a metal material directly contacting the monocrystalline metal silicide material, and a storage device adjacent to the metal material. Electronic devices, electronic systems, and methods of forming an electronic device are also disclosed.”

The patent application was filed on August 13, 2019 (16/539,520).

Tokens to indicate completion of storage
Micron Technology, Inc., Boise, ID, has been assigned a patent (11,151,041) developed by Szubbocsev, Zoltan, Santa Clara, CA, for “tokens to indicate completion of data storage.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Systems, apparatuses, and methods related to tokens to indicate completion of data storage to memory are described. An example method may include storing a number of data values by a first page in a first row of an array of memory cells responsive to receipt of a first command from a host, where the first command is associated with an open transaction token, and receiving a second command from the host to store a number of data values by a second page in the first row. The method may further include sending a safety token to the host to indicate completion of storing the number of data values by the second page in the first row.”

The patent application was filed on October 15, 2019 (16/653,338).

Reflow endurance improvements in triple-level cell NAND flash
Micron Technology, Inc., Boise, ID, has been assigned a patent (11,150,844) developed by Sato, Junichi, Yokohama, Japan, for “reflow endurance improvements in triple-level cell NAND flash.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Disclosed is a memory device and method of operating the same. In one embodiment, a method is disclosed comprising generating compressed data by compressing raw data for storage in a memory device, pre-programming a first region of the memory device with the compressed data, and, in response to detecting that the memory device has powered on, decompressing the compressed data, obtaining the raw data, and transferring the raw data to a second region of the memory device.”

The patent application was filed on February 21, 2019 (16/281,740).

Offsetting capacitance of digit line coupled to storage memory cells coupled to sense amplifier using offset memory cells
Micron Technology, Inc., Boise, ID, has been assigned a patent (11,145,358) developed by Derner, Scott J., Boise, ID, for “offsetting capacitance of a digit line coupled to storage memory cells coupled to a sense amplifier using offset memory cells.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”An apparatus includes a sense amplifier, a plurality of storage memory cells coupled to the sense amplifier via a first digit line, and a plurality of offset memory cells coupled to the sense amplifier via a second digit line. The plurality of storage memory cells and the plurality of offset memory cells can comprise an array of memory cells. Each of the storage memory cells and the offset memory cells can include a respective capacitor having a particular capacitance.”

The patent application was filed on August 16, 2019 (16/543,315).

Temperature-based data storage processing
Micron Technology, Inc., Boise, ID, has been assigned a patent (11,144,452) developed by Sato, Junichi, Yokohama, Japan, for a “temperature-based data storage processing.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data storage device monitors a storage media temperature and adjusts data storage operations of the storage device based on the monitored and/or a predicted future temperature of the storage media. In one approach, data is stored in a first mode (e.g., a TLC mode) in a non-volatile storage media. One or more temperatures associated with the non-volatile storage media are monitored using at least one sensor to collect sensor data. The manner of storage of the data in the storage device is adjusted based on the collected sensor data. The adjusting comprises compressing the data to provide compressed data, and storing the compressed data in a second mode (e.g., an SLC mode) in the non-volatile storage media.”

The patent application was filed on February 5, 2020 (16/783,012).

Logical-to-physical map synchronization in memory
Micron Technology, Inc., Boise, ID, has been assigned a patent (11,138,108) developed by Parry, Jonathan Scott, Boise, ID, and Grosz, Nadav, Broomfield, CO, for a “logical-to-physical map synchronization in a memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Devices and techniques for logical-to-physical (L2P) map (e.g., table) synchronization in a managed memory device are described herein. For example, a plaintext portion of an L2P map may be updated in a managed memory device. In response to updating the plaintext portion of the L2P map, the updated portion can be obfuscated to create an obfuscated version of the updated portion of the L2P map. Both the updated portion and the obfuscated version of the updated portion can be saved in storage of the memory device. When a request from a host for the updated portion of the L2P map is received, the memory device can provide the obfuscated version of the portion from the storage.”

The patent application was filed on August 22, 2019 (16/548,107).

Memory array with access line control having shunt sense line
Micron Technology, Inc., Boise, ID, has been assigned a patent (11,127,436) developed by Li, Jiyun, Boise, ID, for a “memory array with access line control having a shunt sense line.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”An example apparatus includes an array of memory cells. Each memory cell includes an access device. Each access device includes a first source/drain region, a second source/drain region, and a gate opposing a channel connecting the first source/drain region and the second source/drain region. Each access device further includes a storage node. The example apparatus further includes a plurality of sense lines coupled to the first source/drain region of a different respective memory cell of the array of memory cells. The example apparatus further includes a plurality of access lines, wherein each access line includes at least one conductive pathway formed between the access line and a source/drain region of an access device coupled to the access line. The example apparatus further includes a shunt sense line coupled to the additional access device where the conductive pathway is formed.”

The patent application was filed on December 11, 2019 (16/710,687).

Chalcogenide memory components and composition
Micron Technology, Inc., Boise, ID, has been assigned a patent (11,114,615) developed by Varesi, Enrico, Milan, Italy, Fantini, Paolo, Vimercate, Italy, Fratin, Lorenzo, Buccinasco, Italy, and Lengade, Swapnil A., Boise, ID, for “chalcogenide memory device components and composition.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Systems, devices, and methods related to or that employ chalcogenide memory components and compositions are described. A component of a memory cell, such as a selector device, storage device, or self-selecting memory device, may be made of a chalcogenide material composition. A chalcogenide material may have a composition that includes one or more elements from the boron group, such as boron, aluminum, gallium, indium, or thallium. The chalcogenide material, for instance, may have a composition of selenium, germanium, and at least one of boron, aluminum, gallium, indium, or thallium. The chalcogenide material may in some cases also include arsenic, but may in some cases lack arsenic.”

The patent application was filed on June 18, 2020 (16/905,366).

Cross-point memory and methods for forming
Micron Technology, Inc., Boise, ID, has been assigned a patent (11,114,613) developed by Pellizzer, Fabio, Cornate d’Adda, Italy, Tortorelli, Innocenzo, Cernusco sul Naviglio, Italy, and Ghetti, Andrea, Concorezzo, Italy, for “cross-point memory and methods for forming of the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”The disclosed technology generally relates to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. Line stacks are formed, including a storage material line disposed over lower a conductive line. Upper conductive lines are formed over and crossing the line stacks, exposing portions of the line stacks between adjacent upper conductive lines. After forming the upper conductive lines, storage elements are formed at intersections between the lower conductive lines and the upper conductive lines by removing storage materials from exposed portions of the line stacks, such that each storage element is laterally surrounded by spaces. A continuous sealing material laterally surrounds each of the storage elements.”

The patent application was filed on May 4, 2020 (16/866,302).

Predictive data storage hierarchical memory
Micron Technology, Inc., Boise, ID, has been assigned a patent (11,113,193) developed by Korzh, Anton, Boise, ID, for “predictive data storage hierarchical memory systems and methods.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Techniques for implementing an apparatus, which includes a memory system that provides data storage via multiple hierarchical memory levels, are provided. The memory system includes a cache that implements a first memory level and a memory array that implements a second memory level higher than the first memory level. Additionally, the memory system includes one or more memory controllers that determine a predicted data access pattern expected to occur during an upcoming control horizon, based at least in part on first context of first data to be stored in the memory sub-system, second context of second data previously stored in the memory system, or both, and control what one or more memory levels of the multiple hierarchical memory levels implemented in the memory system in which to store the first data, the second data, or both based at least in part on the predicted data access pattern.”

The patent application was filed on May 27, 2020 (16/884,815).

Power optimization for memory subsystems
Micron Technology, Inc., Boise, ID, has been assigned a patent (11,112,982) developed by He Deping, and Palmer, David A., Boise, ID, for a “power optimization for memory subsystems.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A processing device initializes a drive strength value of a storage device in an electronic device to a first level. The processing device detects an operation to be performed on the storage device and executes the operation. The processing device monitors a bit error rate occurring in the storage device as a result of executing the operation and determines if the bit error rate satisfies a threshold value. In response to determining that the bit error rate satisfies the threshold value, the processing device increases the drive strength value of the storage device to a second level and re-executes the operation at the increased drive strength value of the storage device.”

The patent application was filed on August 27, 2019 (16/552,243).

Hierarchical memory
Micron Technology, Inc., Boise, ID, has been assigned a patent (11,106,595) developed by Korzh, Anton, Santa Clara, CA, Ramesh, Vijay S., and Murphy, Richard C., Boise, ID, for “hierarchical memory systems.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Apparatuses, systems, and methods for hierarchical memory systems are described. A hierarchical memory system can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. An example method includes initiating a read request associated with an address from an input/output device, redirecting the read request to a hierarchical memory component, generating, by the hierarchical memory component, an interrupt message to send to a hypervisor, gathering, at the hypervisor, address register access information from the hierarchical memory component, and determining a physical location of data associated with the read request.”

The patent application was filed on August 22, 2019 (16/547,640).

Latency-based scheduling of command processing in storage
Micron Technology, Inc., Boise, ID, has been assigned a patent (11,106,393) developed by Frolikov, Alex, San Jose, CA, for a “latency-based scheduling of command processing in data storage devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A computer system having a host coupled to a storage device via a peripheral component interconnect express bus. The host communicates write commands of low priority to the storage device, which places them in a queue for execution at an idle time. In response to a determination that the storage device is in an idle state, the storage device best accommodates the write commands in the idle queue in connection with housekeeping tasks, such as garbage collection and wear leveling, to best reduce write amplification.”

The patent application was filed on August 8, 2019 (16/535,700).

Log data storage for flash memory
Micron Technology, Inc., Boise, ID, has been assigned a patent (11,100,996) developed by Papa, Paolo, Naples, Italy, Esposito, Luigi, Piano di Sorrento, Italy, Iaculo, Massimo, San Marco Evangelista, Italy, Yuen, Eric Kwok Fung, Dublin, CA, and Perdaems, Gerard J., Boise, ID, for a “log data storage for flash memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Devices and techniques for managing flash memory are disclosed herein. A memory controller may receive a first program request comprising first host data to be written to the flash memory. The flash memory may comprise a number of storage units with each storage unit comprising a number of storage sub-units. If the first host data is less than a remainder threshold, the memory controller may generate a first program data unit comprising the first host data and first log data describing the flash memory. The memory controller may program the program data unit to the first storage unit of the flash memory, where the first log data is written to a first storage sub-unit of the number of storage sub-unit. The memory controller may also store an indication that the first storage sub-unit is invalid.”

The patent application was filed on August 30, 2017 (15/690,889).

Firmware update in storage backed memory
Micron Technology, Inc., Boise, ID, has been assigned a patent (11,099,831) developed by Van Sickle, Gary R., Arden Hills, MN, and Leyda, Jeffery J., Minneapolis, MN, for a “firmware update in a storage backed memory system.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Devices and techniques for firmware update in storage backed memory are disclosed herein. A firmware image can be stored to a volatile portion of the memory package in response to receiving the firmware image via a first interface of the memory package. A save indication can be received at a second interface of the memory package. The firmware image can be transferred from the volatile portion of the memory package to a non-volatile portion of the memory package based on the save indication. A firmware update indication can be received at the second interface. A firmware update of the memory package can be performed based on the firmware update indication.”

The patent application was filed on August 3, 2018 (16/054,125).

NAND unit cells
Micron Technology, Inc., Boise, ID, has been assigned a patent (11,094,707) developed by Ramaswamy, D.V. Nirmal, and Sandhu, Gurtej S., Boise, ID, for “NAND unit cells.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Some embodiments include methods of forming semiconductor constructions. Alternating layers of n-type doped material and p-type doped material may be formed. The alternating layers may be patterned into a plurality of vertical columns that are spaced from one another by openings. The openings may be lined with tunnel dielectric, charge-storage material and blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed within the lined openings. Some embodiments include methods of forming NAND unit cells. Columns of alternating n-type material and p-type material may be formed. The columns may be lined with a layer of tunnel dielectric, a layer of charge-storage material, and a layer of blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed between the lined columns. Some embodiments include semiconductor constructions, and some embodiments include NAND unit cells.”

The patent application was filed on July 18, 2018 (16/039,269).

NAND unit cells
Micron Technology, Inc., Boise, ID, has been assigned a patent (11,094,706) developed by Ramaswamy, D. V. Nirmal, and Sandhu, Gurtej S., Boise, ID, for “NAND unit cells.“

The patent application was filed on July 18, 2018 (16/039,236).

Performance allocation among users for accessing NVM
Micron Technology, Inc., Boise, ID, has been assigned a patent (11,093,140) developed by Frolikov, Alex, San Jose, CA, for a “performance allocation among users for accessing non-volatile memory devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A computer having a plurality of accounts and a storage device having a host interface, a controller, non-volatile storage media, and firmware. An account is configured with at least a predetermined speed in accessing the non-volatile storage media by allocating a number of input/output submission queues in the buffer area of the host. The number can be determined from a ratio between the predetermined speed configured for the account and a saturated speed of the storage device with sufficient submission queues. Data access requests from the account are evenly distributed to the submission queues allocated for the exclusive use by the account, and the controller, configured via the firmware, processes with equal priority the submission queues configured for the storage device. Thus, the account can have at least the predetermined speed in accessing the non-volatile storage media, regardless of how other accounts access the storage device.”

The patent application was filed on January 19, 2018 (15/875,944).

Multifunctional memory cells
Micron Technology, Inc., Boise, ID, has been assigned a patent (11,087,842) developed by Bhattacharyya, Arup, Essex Junction, VT, for “multifunctional memory cells.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”The present disclosure includes multifunctional memory cells. A number of embodiments include a charge transport element having an oxygen-rich silicon oxynitride material, a volatile charge storage element configured to store a first charge transported through the charge transport element, and a non-volatile charge storage element configured to store a second charge transported through the charge transport element, wherein the non-volatile charge storage element includes a gallium nitride material.”

The patent application was filed on August 9, 2019 (16/536,829).

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