Floadia Assigned Two Patents

Nonvolatile semiconductor storage
Floadia Corp., Tokyo, Japan, has been assigned a patent (11,127,469) developed by Yoshida, Shinji, Yanagisawa, Kazumasa, Sato, Shuichi, and Taniguchi, Yasuhiro, Kodaira, Japan, for a “nonvolatile semiconductor storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A non-volatile semiconductor memory device that achieves downsizing as compared to conventional cases is disclosed. A non-volatile semiconductor memory device has a configuration in which a memory cell is disposed between a programming bit line and a reading bit line. The reading bit line provided between adjacent memory cells is shared by the adjacent memory cells. This configuration of the non-volatile semiconductor memory device, in which the reading bit line is shared by the adjacent memory cells, leads to reduction of the number of reading bit lines as compared to that in a conventional configuration, and further leads to reduction of the area of a control circuit and a sense amplifier circuit connected with the reading bit line, thereby achieving downsizing as compared to conventional cases accordingly.”

The patent application was filed on February 5, 2018 (16/491,704).

Memory cell, nonvolatile semiconductor storage, and method for manufacturing
Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China, has been assigned a patent (11,011,530) developed by Okada, Daisuke, Yanagisawa, Kazumasa, Owada, Fukuo, Yoshida, Shoji, Kawashima, Yasuhiko, Yoshida, Shinji, Taniguchi, Yasuhiro, and Okuyama, Kosuke, Kodaira, Japan, for “memory cell, nonvolatile semiconductor storage device, and method for manufacturing nonvolatile semiconductor storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “When a memory cell (MC) is downsized by reducing the distance between a drain region (12a) and a source region (12b) on the surface of a fin (S2) with a high impurity concentration inside the fin (S2), the shape of the fin (S2) can be set such that a potential difference between a memory gate electrode (MG) and the fin (S2) is reduced to suppress the occurrence of disturbance. Accordingly, the memory cell (MC) achieves downsizing and suppression of the occurrence of disturbance.“

The patent application was filed on June 7, 2019 (16/434,373).