R&D: Embedded NAND Flash-Based Compute-In-Memory Array Demonstrated in Standard Logic Process
Work represents first physical demonstration of embedded NAND flash-based compute-in-memory chip in standard logic process.
This is a Press Release edited by StorageNewsletter.com on October 22, 2021 at 2:30 pmIEEE Journal of Solid-State Circuits has published an article written by Minsu Kim, Muqing Liu, Luke R. Everson and Chris H. Kim, Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 USA.
Abstract: “A neural network hardware inspired by the 3-D NAND flash array structure was experimentally demonstrated in a standard 65-nm CMOS process. Logic-compatible embedded flash memory cells were used for storing multi-level synaptic weights while a bit-serial architecture enables 8 bit x 8 bit multiply-and-accumulate operation. A novel back-pattern tolerant program-verify scheme reduces the cell current variation to less than 0.6 μA. Positive and negative weights are stored in adjacent bitlines, generating a differential output signal. Our eNAND-based neural network core achieves a 98.5% handwritten digit recognition accuracy which is within 0.5% of the software accuracy for the same weight precision. To the best of our knowledge, this work represents the first physical demonstration of an embedded NAND flash-based compute-in-memory chip in a standard logic process.“
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