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R&D: Low Bit-Width LDPC Min-Sum Decoding Scheme for NAND Flash

Simulation shows that approach achieves lower uncorrectable bit error rate with negligible increase in computational complexity, especially with low precision input log-likelihood ratio.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems has published an article written by Lanlan Cui, Wuhan National Laboratory for Optoelectronics, School of Computer Science and Technology, Huazhong University of Science and Technology, Wuhan 430074, China, Xiaojian Liu, DERA Co., Ltd, Shanghai 200050, China, Fei Wu, Wuhan National Laboratory for Optoelectronics, School of Computer Science and Technology, Huazhong University of Science and Technology, Wuhan 430074, China, Zhonghai Lu, School of Electrical Engineering and Computer Science, KTH Royal Institute of Technology, Stockholm 16440, Sweden, and Changsheng Xie, Wuhan National Laboratory for Optoelectronics, School of Computer Science and Technology, Huazhong University of Science and Technology, Wuhan 430074, China.

Abstract: For NAND flash memory, designing a good low-density parity-check (LDPC) decoding algorithm could ensure data reliability. When the decoding algorithm is implemented in hardware, it is necessary to achieve attractive trade off between implementation complexity and decoding performance. In this paper, a novel low bit-width decoding scheme is introduced. In this scheme, the Quasi-Cyclic LDPC (QC-LDPC) is used, and the row-layered normalized min-sum algorithm is improved by restricting the amplitude of minimum and second-minimum values in each check node (CN) updating. The simulation shows that our approach achieves a lower UBER (Uncorrectable Bit Error Rate) with a negligible increase in computational complexity, especially with low precision input log-likelihood ratio (LLR).

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