R&D: Charge Trap Modeling Based on Mobility–Lifetime Product for NAND Flash Program Operation

Japanese Journal of Applied Physics has published an article written by Geon Woong Kim, and Seung Jae Baik, School of Electronic and Electrical Engineering, Hankyong National University, Gyeonggi-do 17579, Republic of Korea.

Abstract: “High-density development of 3D NAND flash is based on increasing the height of memory cell stacking, which continuously increases fabrication difficulty. It is thus necessary to develop a unit cell scaling technology to reduce the fabrication difficulty. The future direction of unit cell scaling should be based on the development of material with high dielectric constants. In developing new materials, predictable simulation models are required to facilitate practical device development. In this study, we present a model to simulate programming characteristics, where the mobility–carrier-lifetime (μτ) product represents the charge-trapping efficiency of charge trap dielectric films. The average distance from the tunneling layer of trapped charges is assumed to be proportional to the electric field in the trap layer, which is a consequence of the μτ parameterization. The simulated trapped charge distribution indicates that the average trap distance moves closer to the tunnel layer as the program time elapses. Additionally, the program window increases as the average trap distance decreases. A new trap layer material that would replace conventional Si₃N₄ needs to have a μτ lower than 5 × 10⁻¹⁵ cm² V⁻¹.“