R&D: SecNVM, Power Side-Channel Elimination Using On-Chip Capacitors for Highly Secure Emerging NVM

IEEE Xplore has published an article written by Karthikeyan Nagarajan, Pennsylvania State University, University Park, PA, USA, Farid Uddin Ahmed, University of Missouri-Kansas City, Kansas City, MO, USA, Mohammad Nasim Imtiaz Khan, Pennsylvania State University, University Park, PA, USA, Asmit De, Pennsylvania State University, University Park, PA, USA, Masud H. Chowdhury, University of Missouri-Kansas City, Kansas City, MO, USA,and Swaroop Ghosh, Pennsylvania State University, University Park, PA, USA.

Abstract: “Emerging nonvolatile memories (NVMs), such as resistive RAM (RRAM) and spin-transfer-torque RAM (STTRAM), present exciting opportunities for data storage applications and offer improved access speeds, retention times, power consumption, and scalability. However, these technologies leak the Hamming weight of data through power side-channel during read and write operations. We propose a technique leveraging on-chip capacitor and voltage regulator (VR) that powers the NVM read/write operations. The side-channel leakage is eliminated due to the isolation of memory array from the external power supply during read/write operations. The residual charge on capacitor bank is discarded safely to prevent information leakage during capacitor recharging. The VR ensures a steady voltage during the entire read/write operations even though the capacitor discharges. The design presents a performance (instructions per cycle) degradation of 0.53%–1.2% under parsec and splash-2 benchmarks and incurs an area overhead of ∼3.54×10⁻⁵ % and an energy overhead of ∼3.05×10⁻⁵ % for a 4-Mb RRAM memory array. For a 64-bit word, the design improves security by 2.7 ×10¹⁹× to 2⁶⁴× . SecNVM should be used in small security-critical memory macros to limit the overhead. SecNVM is generic and could protect any security module such as encryption engines, against power side-channel attacks.“