Micron Technology Assigned Twenty-Five Patents

Apparatuses including memory cells with gaps comprising low dielectric constant materials
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,985,251) developed by Lee, Minsoo, Boise, ID, and Goda, Akira, Setagaya, Japan, for “apparatuses including memory cells with gaps comprising low dielectric constant materials.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Various embodiments include apparatuses and methods of forming the same. One such apparatus can include a first dielectric material and a second dielectric material, and a conductive material between the first dielectric material and the second dielectric material. A charge storage element, such as a floating gate or charge trap, is between the first dielectric material and the second dielectric material and adjacent to the conductive material. The charge storage element has a first surface and a second surface. The first and second surfaces are substantially separated from the first dielectric material and the second dielectric material, respectively, by a first air gap and a second air gap. Additional apparatuses and methods are disclosed.”

The patent application was filed on May 11, 2020 (Appl. No.16/871,600).

Secure memory device with unique identifier for authentication
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,984,136) developed by Dover, Lance W., Fair Oaks, CA, for a “secure memory device with unique identifier for authentication.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A secure memory device for secure data storage and related method are provided. The device may include an accessible data storage area configured to store data, a start location register that points to a start of the accessible data storage area, and a size-related register that allows a size of the accessible data storage area to be determined. A secret area comprises a device secret that is a value unique to the device, and that is not accessible from external to the device, and is accessible under at least one predefined conditions internal to the device, an access control element configured to prevent external access to the secret data. A generator generates a derived secret based on the storage data and the secret data that is usable to authenticate the storage data. The device may also include a memory bus over which the derived secret is communicated.”

The patent application was filed on August 31, 2017 (Appl. No.15/693,071).

Hybrid logical to physical caching scheme
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,983,918) developed by Manganelli, Carminantonio, Benevento, Italy, Weinberg, Yoav, Ontario, CA, Sassara, Alberto, Papa, Paolo, Naples, Italy, Esposito, Luigi, Piano di Sorrento, Italy, D’Eliseo, Giuseppe, Caserta, Italy, Della Monica, Angelo, Casaluce, Italy, and Iaculo, Massimo, San Marco Evangelista, Italy, for a “hybrid logical to physical caching scheme.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A variety of applications can include systems and methods that utilize a hybrid logical to physical (L2P) caching scheme. A L2P cache and a L2P changelog in a storage device can be controlled for use in write and read operations of a memory system. A page pointer table in the L2P cache can be accessed, for performance of a write operation in the memory system, to obtain a specific physical address mapped to a specified logical block address from a host, where the access is based on the page pointer table loaded into the L2P cache from the L2P changelog. The L2P cache area can be progressively configured with the most frequently accessed page pointer tables in the L2P changelog in the latest host accesses.”

The patent application was filed on March 6, 2019 (Appl. No.16/294,427).

Dynamic size of static SLC cache
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,983,829) developed by Luo, Xiangang, Fremont, CA, and Huang, Jianmin, San Carlos, CA, for a “dynamic size of static SLC cache.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Apparatus and methods are disclosed, including using a memory controller to track a maximum logical saturation over the lifespan of the memory device, where logical saturation is the percentage of capacity of the memory device written with data. A portion of a pool of memory cells of the memory device is reallocated from single level cell (SLC) static cache to SLC dynamic cache storage based at least in part on a value of the maximum logical saturation, the reallocating including writing at least one electrical state to a register, in some examples.”

The patent application was filed on July 12, 2019 (Appl. No.16/510,526).

Epitaxial growth on semiconductor structures
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,978,295) developed by Yang, Guangjun, Meridian, ID, and Tapias, Nicholas R., Boise, ID, for a “epitaxial growth on semiconductor structures.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Systems, apparatuses, and methods related to epitaxial growth on semiconductor structures are described. An apparatus may include a working surface of a substrate material and a storage node connected to an active area of an access device on the working surface. The apparatus may also include a material epitaxially grown over the storage node contact to enclose a non-solid space between the storage node contact and passing sense lines.”

The patent application was filed on June 19, 2019 (Appl. No.16/445,507).

Hybrid memory system interface
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,977,198) developed by Caraccio, Danilo, Milan, Italy, Dallabora, Marco, Melegnano, Italy, Balluchi, Daniele, Cernusco Sul Naviglio, Italy, Amato, Paolo, Treviglio, Italy, and Porzio, Luca, Casalnuovo di Napoli, Italy, for a “hybrid memory system interface.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”The present disclosure includes apparatuses and methods related to a hybrid memory system interface. An example computing system includes a processing resource and a storage system coupled to the processing resource via a hybrid interface. The hybrid interface can provide an input/output (I/O) access path to the storage system that supports both block level storage I/O access requests and sub-block level storage I/O access requests.”

The patent application was filed on September 12, 2018 (Appl. No.16/128,882).

Memory device with dynamic storage mode control
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,977,173) developed by Li, Yun, Muchherla, Kishore Kumar, Fremont, CA, Feeley, Peter, Boise, ID, Malshe, Ashutosh, Fremont, CA, Hubbard, Daniel J., Hale, Christopher S., Brandt, Kevin R., and Ratnam, Sampath K., Boise, ID, for a “memory device with dynamic storage mode control.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory system includes: a memory array including a plurality of memory cells, the plurality of memory cells including a plurality of cache memory cells, and a controller coupled to the memory array, the controller configured to: track usage of a first subset of the plurality of cache memory cells operating in a single-level cell, SLC) mode, wherein the tracking includes monitoring for an idle time event, and designate a storage mode for a second subset of the plurality of cache memory cells based on the tracked usage of the first subset, wherein the storage mode determines a storage density to be used for data writes.”

The patent application was filed on October 22, 2018 (Appl. No.16/167,345).

Forming NAND cell units
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,971,607) developed by Hu, Yongjun Jeff, Boise, ID, for “methods of forming NAND cell units.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures.”

The patent application was filed on August 22, 2019 (Appl. No.16/548,003).

Shared parity protection
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,970,170) developed by Parry, Jonathan Scott, and Cariello, Giuseppe, Boise, ID, for a “shared parity protection.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A variety of applications can include apparatus and/or methods that provide shared parity protection to data in memory devices of a memory system. Parity data of different data streams programmed into different blocks of one or more memory devices can be overlapped and wrapped into slots of a volatile memory arranged as a storage device for the parity data. A parity map of parity-to-data reflecting the overlapping of the parity data can be maintained in the volatile memory along with the overlapped parity. The parity map can be updated as parity data is generated from further programming of the data streams. The parity contents of the volatile memory, including the parity map, can be transferred to a non-volatile memory in response to a determination of an occurrence of a transfer criterion. The parity contents flushed to the non-volatile memory can be used to allow correct data reconstruction in case of failures in programming.”

The patent application was filed on August 29, 2019 (Appl. No.16/555,014).

Namespaces allocation in non-volatile memory devices
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,969,963) developed by Frolikov, Alex, San Jose, CA, for “namespaces allocation in non-volatile memory devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A computer storage device having a host interface, a controller, non-volatile storage media, and firmware. The firmware instructs the controller to: receive, via the host interface, a request from a host to allocate a namespace of a quantity of non-volatile memory, generate, in response to the request, a namespace map identifying a plurality of blocks of addresses having a same predetermined block size, and a partial block of addresses having a size smaller than the predetermined block size, and convert, using the namespace map, logical addresses in the namespace communicated from the host to physical addresses for the quantity of the non-volatile memory. For example, the request for allocating the namespace can be in accordance with an NVMe protocol.”

The patent application was filed on July 23, 2019 (Appl. No.16/520,204).

Memory read apparatus
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,964,400) developed by Tanzawa, Toru, Tokyo, Japan, for “memory read apparatus and methods.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Apparatus and methods are disclosed, including a method that raises an electrical potential of a plurality of access lines to a raised electrical potential, where each access line is associated with a respective charge storage device of a string of charge storage devices. The electrical potential of a selected one of the access lines is lowered, and a data state of the charge storage device associated with the selected access line is sensed while the electrical potential of the selected access line is being lowered. Additional apparatus and methods are described.”

The patent application was filed on February 25, 2020 (Appl. No.16/800,530).

Assemblies having conductive structures with three or more different materials
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,957,775) developed by Economy, David Ross, Klein, Rita J., Greenlee, Jordan D., Meldrim, John Mark, Kraus, Brenda D., Boise, ID, and McTeer, Everett A., Eagle, ID, for “assemblies having conductive structures with three or more different materials.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.”

The patent application was filed on July 1, 2019 (Appl. No.16/458,400).

Shared error check and correct logic for multiple data banks
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,957,413) developed by Takahashi, Susumu, and Fujisawa, Hiroki, Kanagawa, Japan, for “shared error check and correct logic for multiple data banks.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Systems and methods related to memory devices that may perform error check and correct (ECC) functionality. The systems and methods may employ ECC logic that may be shared between two or more banks. The ECC logic may be used to perform memory operations such as read, write, and masked-write operations, and may increase reliability of storage data.”

The patent application was filed on October 31, 2018 (Appl. No.16/176,952).

Multifunctional memory cells
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,957,389) developed by Bhattacharyya, Arup, Essex Junction, VT, for “multifunctional memory cells.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”The present disclosure includes multifunctional memory cells. A number of embodiments include a gate element, a charge transport element, a first charge storage element configured to store a first charge transported from the gate element and through the charge transport element, wherein the first charge storage element includes a nitride material, and a second charge storage element configured to store a second charge transported from the gate element and through the charge transport element, wherein the second charge storage element includes a gallium nitride material.”

The patent application was filed on January 16, 2020 (Appl. No.16/744,388).

Metadata grouping for un-map techniques
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,957,381) developed by Palmer, David Aaron, Boise, ID, for “metadata grouping for un-map techniques.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Devices and techniques are disclosed herein to address high latency associated with large-scale un-map or trim commands associated with flash memory. In an example, a method can include receiving a trim command for a partition of a storage system, identifying a record of a partition table of the storage system corresponding to the partition, updating a partition count of the record with a count value of a partition counter of the storage system, and incrementing the partition counter.”

The patent application was filed on August 28, 2019 (Appl. No.16/553,358).

Responding to changes in available power supply
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,950,313) developed by Trivedi, Avani F., Eagle, ID, Evans, Tracy D., Christensen, Carla L., Boise, ID, Iwasaki, Tomoko Ogura, San Jose, CA, and Limaye, Aparna U., Boise, ID, for “responding to changes in available power supply.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Methods of operating a memory having a first pool of memory cells having a first storage density and a second pool of memory cells having a second storage density greater than the first storage density, as well as apparatus configured to perform similar methods, might include determining whether a value of an indication of available power is less than a threshold, and, in response to determining that the value of the indication of available power is less than the threshold, increasing a size of the first pool of memory cells, limiting write operations of the memory to the first pool of memory cells, and postponing movement of data from the first pool of memory cells to the second pool of memory cells.”

The patent application was filed on August 28, 2019 (Appl. No.16/553,241).

Storage device operation orchestration
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,949,101) developed by Murphy, Richard C., Hush, Glen E., Ramesh, Vijay S., Boise, ID, Porterfield, Allan, Durham, NC, and Korzh, Anton, Boise, ID, for a “storage device operation orchestration.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Systems, apparatuses, and methods related to storage device operation orchestration are described. A plurality of computing devices (or ‘tiles’) can be coupled to a controller (e.g., an ‘orchestration controller’) and an interface. The controller can control operation of the computing devices. For instance, the controller can include circuitry to request a block of data from a memory device coupled to the apparatus, cause a processing unit of at least one computing device of the plurality of computing devices to perform an operation on the block of data in which at least some of the data is ordered, reordered, removed, or discarded, and cause, after some of the data is ordered, reordered, removed, or discarded, the block of data to be transferred to the interface coupled to the plurality of computing devices.”

The patent application was filed on February 25, 2019 (Appl. No.16/284,273).

Integrated memory having body region comprising different semiconductor
composition than source/drain region
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,943,915) developed by Karda, Kamal M., Fayrushin, Albert, Liu, Haitao, and Prall, Kirk D., Boise, ID, for an “integrated memory having the body region comprising a different semiconductor composition than the source/drain region.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Some embodiments include an assembly having a memory cell with an active region which includes a body region between a pair of source/drain regions. A charge-storage material is adjacent to the body region. A conductive gate is adjacent to the charge-storage material. A hole-recharge arrangement is configured to replenish holes within the body region during injection of holes from the body region to the charge-storage material. The hole-recharge arrangement includes a heterostructure active region having at least one source/drain region of a different composition than the body region, and/or includes an extension coupling the body region with a hole-reservoir. A wordline is coupled with the conductive gate. A first comparative digit line is coupled with one of the source/drain regions, and a second comparative digit line is coupled with the other of the source/drain regions.”

The patent application was filed on August 27, 2019 (Appl. No.16/552,257).

Mitigation of voltage threshold drift associated with power down condition of NVM device
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,943,657) developed by Sarpatwari, Karthik, Pellizzer, Fabio, Chen, Jessica, and Gajera, Nevil, Meridian, ID, for a “mitigation of voltage threshold drift associated with power down condition of non-volatile memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Methods, systems, and devices for dirty write on power off are described. In an example, the described techniques may include writing memory cells of a device according to one or more parameters (e.g., reset current amplitude) where each memory cell is associated with a storage element storing a value based on a material property associated with the storage element. Additionally, the described techniques may include identifying, after writing the memory cells, an indication of power down for the device and refreshing, before the power down of the device, a portion of the memory cells based on identifying the indication of the power down for the device. In some cases, refreshing includes modifying at least one of the one or more parameters for a write operation for the portion of the memory cells.”

The patent application was filed on August 19, 2019 (Appl. No.16/544,669).

Memory tile access and selection patterns
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,942,873) developed by Castro, Hernan A., Shingle Springs, CA, Tedrow, Kerry Dean, Folsom, CA, and Wu, Jack Chinho, San Jose, CA, for “memory tile access and selection patterns.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile has an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors. The selection circuitry includes line drivers that select a storage component of a memory tile based on a corresponding digit line conductor and a corresponding access line conductor to the storage component. The selection circuitry may select two or more storage components of a memory tile in a consecutive manner before selecting the storage components of a different memory tile.”

The patent application was filed on July 9, 2019 (Appl. No.16/506,650).

Programmable charge-storage transistor, array of elevationally-extending strings
of memory cells, and method of forming
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,937,904) developed by Liu, Haitao, Karda, Kamal M., and Fayrushin, Albert, Boise, ID, for “programmable charge-storage transistor, an array of elevationally-extending strings of memory cells, and a method of forming an array of elevationally-extending strings of memory cells.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A programmable charge-storage transistor comprises channel material, insulative charge-passage material, charge-storage material, a control gate, and charge-blocking material between the charge-storage material and the control gate. The charge-blocking material comprises a non-ferroelectric insulator material and a ferroelectric insulator material. Arrays of elevationally-extending strings of memory cells of memory cells are disclosed, including methods of forming such. Other embodiments, including method, are disclosed.”

The patent application was filed on February 7, 2018 (Appl. No.15/890,530).

Three dimensional memory arrays
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,937,829) developed by Pirovano, Agostino, Milan, Italy, Redaelli, Andrea, Casatenovo, Italy, Pellizzer, Fabio, Boise, ID, and Tortorelli, Innocenzo, Cernusco sul Naviglio, Italy, for “three dimensional memory arrays.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”In an example, a memory array may include a plurality of first dielectric materials and a plurality of stacks, where each respective first dielectric material and each respective stack alternate, and where each respective stack comprises a first conductive material and a storage material. A second conductive material may pass through the plurality of first dielectric materials and the plurality of stacks. Each respective stack may further include a second dielectric material between the first conductive material and the second conductive material.”

The patent application was filed on August 26, 2019 (Appl. No.16/550,532).

Variable read error code correction
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,931,307) developed by Luo, Xiangang, Fremont, CA, and Luo, Ting, Santa Clara, CA, for a “variable read error code correction.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Devices and techniques for variable read throughput control in a storage device are described herein. Bits from can be received for a read that is one of several types assigned to reads. A low-density parity-check (LDPC) iteration maximum can be set based on the type. LDPC iterations can be performed up to the LDPC iteration maximum and a read failure signaled in response to the LDPC iterations reaching the LDPC iteration maximum.”

The patent application was filed on December 28, 2018 (Appl. No.16/235,171).

Memory device with split pillar architecture
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,930,707) developed by Fratin, Lorenzo, Buccinasco, Italy, Pellizzer, Fabio, Boise, ID, and Fantini, Paolo, Vimercate, Italy, for a “memory device with a split pillar architecture.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Methods, systems, and devices for memory device with a split pillar architecture are described. A memory device may include a substrate arranged with conductive contacts in a pattern and openings through alternative layers of conductive and insulative material that may decrease the spacing between the openings while maintaining a dielectric thickness to sustain the voltage to be applied to the array. After etching material, an insulative material may be deposited in a trench. Portions of the insulative material may be removed to form openings, into which cell material is deposited. Conductive pillars may extend perpendicular to the planes of the conductive material and the substrate, and couple to conductive contacts. The conductive pillars and cell material may be divided to form a first and second storage components and first and second pillars.”

The patent application was filed on July 2, 2019 (Appl. No.16/460,884).

Enhanced flush transfer efficiency via flush prediction
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,930,354) developed by Palmer, David Aaron, Boise, ID, for an “enhanced flush transfer efficiency via flush prediction.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Devices and techniques for enhanced flush transfer efficiency via flush prediction in a storage device are described herein. User data from a user data write can be stored in a buffer. The size of the user data stored in the buffer can be smaller than a write width for a storage device subject to the write. This size difference results in buffer free space. A flush trigger can be predicted. Additional data can be marshaled in response to the prediction of the flush trigger. The size of the additional data is less than or equal to the buffer free space. The additional data can be stored in the buffer free space. The contents of the buffer can be written to the storage device in response to the flush trigger.”

The patent application was filed on February 24, 2020 (Appl. No.16/799,490).