STMicroelectronics Assigned Six Patents

Non-volatile memory data bus
STMicroelectronics (Rousset) SAS, Rousset, France, has been assigned a patent (11,056,180) developed by La Rosa, Francesco, Rousset, France, for a “non-volatile memory data bus.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A non-volatile memory integrated circuit has a memory plane organized into rows and into columns containing bit lines. The read amplifiers for each bit line are configured to generate an output signal on a read data channel. The read data channels respectively run through the memory plane along each bit line. Each read data channel is connected to all of the read amplifiers of the respective bit line.”

The patent application was filed on April 20, 2020 (16/853,036).

Access to memory
STMicroelectronics (Rousset) SAS, Rousset, FR), and STMicroelectronics (Grenoble 2) SAS, Grenoble, France, has been assigned a patent (11,055,237) developed by Daineche, Layachi, Boue-bel-Air, France, Chbani, Xavier, Grenoble, France, and Van-Den-Bossche, Nadia, Meylan, France, for a “method of access to a memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”In a non-volatile memory of a microcontroller, first information representative of a value selected among at least four values is stored. Furthermore, for each of a plurality of areas of the memory, second information representative of a type selected among two types is also stored. Access to each of the areas is conditioned according to the selected value and to the type of the area.”

The patent application was filed on October 7, 2019 (16/594,210).

Programming phase-change memory of differential type
STMicroelectronics S.r.l., Agrate Brianza, Italy, has been assigned a patent (11,049,561) developed by Disegni, Fabio Enrico Carlo, Spino d’adda, Italy, Goller, Federico, Turin, Italy, Torti, Cesare, Pavia, Italy, Carissimi, Marcella, Treviolo, Italy, and Calvetti, Emanuela, Villa d’adda, Italy, for “method for programming a phase-change memory device of differential type, memory device, and electronic system.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A method for programming a phase-change-memory device of a differential type comprises, in a first programming mode, supplying, during a first time interval, a same first programming current, of a type chosen between a SET current and a RESET current, to all the direct and complementary memory cells that are to be programmed with said first programming current, and, in a second programming mode, supplying, during a second time interval, a same second programming current, of the other type chosen between a SET current and a RESET current, to all the direct and complementary memory cells that are to be programmed with said second programming current, thus completing, in just two time steps, writing of a logic word in the memory device.”

The patent application was filed on June 16, 2020 (16/903,264).

Phase-change memory cell having compact structure
STMicroelectronics (Crolles 2) SAS, Crolles, France, and STMicroelectronics (Rousset) SAS, Rousset, France, has been assigned a patent (11,031,550) developed by Boivin, Philippe, Venelles, France, and Jeannot, Simon, Grenoble, France, for a “phase-change memory cell having a compact structure.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.”

The patent application was filed on June 28, 2019 (16/457,855).

Electronic device including digital circuit for accessing encrypted data in memory
STMicroelectronics S.r.l. (Agrate Brianza, Italy) and STMicroelectronics (Rousset) SAS, Rousset, France, has been assigned a patent (11,023,566) developed by Lunghi, Stefano, Azzate, Italy, and Martinez, Albert, Bouc Bel Air, France, for “electronic device including a digital circuit for accessing encrypted data in a memory and corresponding method to access encrypted data in a memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”An electronic device includes: a non-volatile memory configured to store data including encrypted data, and a digital circuit. The digital circuit includes: a microprocessor configured to access the non-volatile memory and an internal memory, and a decryption circuit arranged on an interconnect network identifying an internal data path for exchanging the data between the non-volatile memory and the microprocessor, and connected to a memory controller of the non-volatile memory for receiving blocks of data from the non-volatile memory, the decryption circuit being configured to: perform a decryption on the fly of blocks of the data read from the non-volatile memory to obtain read decrypted data, generate first decryption masks corresponding to first blocks of data being read from the non-volatile memory at a given read address, and generate second decryption masks corresponding to second blocks of data to be read from the non-volatile memory at a next estimated read address.”

The patent application was filed on October 3, 2018 (16/150,810).

Non-volatile memory device with vertical state transistor and vertical selection transistor
STMicroelectronics (Rousset) SAS, Rousset, France, has been assigned a patent (10,991,710) developed by Hubert, Quentin, Marseilles, France, Marzaki, Abderrezak, Aix en Provence, France, and Delalleau, Julien, Marseilles, France , for “non-volatile memory device with vertical state transistor and vertical selection transistor.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A non-volatile memory device includes a vertical state transistor disposed in a semiconductor substrate, where the vertical state transistor is configured to trap charges in a dielectric interface between a semiconductor well and a control gate. A vertical selection transistor is disposed in the semiconductor substrate. The vertical selection transistor is disposed under the state transistor, and configured to select the state transistor.”

The patent application was filed on April 23, 2019 (16/391,768).