SanDisk Technologies/WD Assigned Twenty Four Patents

One selector one resistor MRAM crosspoint memory array fabrication
SanDisk Technologies LLC, Addison, TX, a Western Digital Corp company, has been assigned a patent (11,056,534) developed by Wan, Lei, Wu, Tsai-Wei, San Jose, CA, and Katine, Jordan A., Mountain View, CA, for “one selector one resistor MRAM crosspoint memory array fabrication methods.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory array is provided that includes a first memory level having a plurality of memory cells each including a corresponding magnetic memory element coupled in series with a corresponding selector element, and a plurality of vias, each of the vias coupled in series with a corresponding one of the memory cells.”

The patent application was filed on July 2, 2019 (16/460,820).

Three-dimensional memory containing epitaxial ferroelectric memory elements
SanDisk Technologies LLC, Addison, TX, a Western Digital Corp company, has been assigned a patent (11,049,880) developed by Rajashekhar, Adarsh, Santa Clara, CA, Zhou, Fei, San Jose, CA, Sharangpani, Rahul, Fremont, CA, and Makala, Raghuveer S., Campbell, CA, for “three-dimensional memory device containing epitaxial ferroelectric memory elements and methods for forming the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack. Each of the memory stack structures includes a vertical stack of single crystalline ferroelectric dielectric layers and a respective vertical semiconductor channel.”

The patent application was filed on August 2, 2019 (16/530,256).

Three-dimensional memory containing through-memory-level contact via structures
SanDisk Technologies LLC, Addison, TX, a Western Digital Corp company, has been assigned a patent (11,049,876) developed by Kaminaga, Michimoto, Nagoya, Japan, and Cui, Zhixin, Yokkaichi, Japan, for a “three-dimensional memory device containing through-memory-level contact via structures.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A contact via structure vertically extending through an alternating stack of insulating layers and electrically conductive layers is provided in a staircase region having stepped surfaces. The contact via structure is electrically isolated from each electrically conductive layer of the alternating stack except for an electrically conductive layer that directly underlies a horizontal interface of the stepped surfaces. A laterally-insulated structure includes a conductive via structure having an upper conductive via portion overlying and contacting an annular area of a top surface of one of the electrically conductive layers, a lower conductive via portion having a lesser lateral dimension than the upper conductive via portion and extending through at least a bottommost one of the electrically conductive layers, and an interconnection conductive via portion located between the upper conductive via portion and the lower conductive via portion and contacting a cylindrical sidewall of the one of the electrically conductive layers.”

The patent application was filed on May 22, 2020 (16/881,353).

Three-dimensional memory device containing tubular blocking dielectric spacers
SanDisk Technologies LLC, Addison, TX, a Western Digital Corp company, has been assigned a patent (11,049,807) developed by Li, Li, Nagoya, Japan, Kasai, Yuki, Kuwana, Japan, and Hinoue, Tatsuya, Yokkaichi, Japan, for a “three-dimensional memory device containing tubular blocking dielectric spacers.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings are formed through the alternating stack. Annular recesses are formed by laterally recessing the sacrificial material layers around each memory opening. A tubular aluminum oxide spacer is formed at a periphery of each annular recess. A tubular silicon oxycarbide spacer is selectively deposited on each of the tubular aluminum oxide spacers. The tubular silicon oxycarbide spacers are converted into tubular silicon oxide spacers by an oxidation process. Tubular charge storage spacers are formed on inner sidewalls of the tubular silicon oxide spacers. A vertical semiconductor channel is formed over a respective vertical stack of tubular charge storage spacer within each memory opening. The sacrificial material layers are removed to form backside recesses. Electrically conductive material are deposited in the backside recesses to form electrically conductive layers.”

The patent application was filed on September 25, 2019 (16/582,262).

Modulation of programming voltage during cycling
SanDisk Technologies LLC, Addison, TX, a Western Digital Corp company, has been assigned a patent (11,049,580) developed by Gautam, Rajdeep, and Oowada, Ken, Yokohama, Japan, for a “modulation of programming voltage during cycling.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Systems and methods for increasing cycling endurance and minimizing over programming of non-volatile memory cells by modulating the programming voltage applied to the non-volatile memory cells over time as the number of program/erase cycles increases are described. A bit count ratio based on bit counts within two threshold voltage zones may be used to determine the amount of voltage reduction in the programming voltage applied during subsequent programming operations. For example, if the bit count ratio is between 0.02 and 0.05, then the reduction in the programming voltage may be 100 mV, if the bit count ratio is between 0.05 and 0.10, then the reduction in the programming voltage may be 200 mV. The modulation (e.g., the reduction) of the programming voltage may be performed at varying cycle intervals depending on the total number of program/erase cycles for a memory block and/or the bit count ratio.”

The patent application was filed on June 28, 2020 (16/914,408).

Non-volatile memory with program verify skip
SanDisk Technologies LLC, Addison, TX, a Western Digital Corp company, has been assigned a patent (11,049,578) developed by Murai, Shota, Fujisawa, Japan, and Chin, Henry, Fremont, CA, for a “non-volatile memory with program verify skip.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Non-volatile memory cells are programmed by applying a programming signal as a series of programming voltage pulses (or other doses of programming) to selected memory cells and verifying the memory cells between programming voltage pulses. To achieve tighter threshold voltage distributions, a coarse/fine programming process is used that includes a two step verification between programming voltage pulses comprising an intermediate verify condition and a final verify condition. Memory cells being programmed that have reached the intermediate verify condition are slowed down for further programming. Memory cells being programmed that have reached the final verify condition are inhibited from further programming. To reduce the number of verify operations performed, a system is proposed for skipping verification at the intermediate verify condition for some programming voltage pulses and skipping verification at the final verify condition for some programming voltage pulses.”

The patent application was filed on February 19, 2020 (16/795,313).

Three-dimensional memory with depletion region position control and erasing same using gate induced leakage
SanDisk Technologies LLC, Addison, TX, a Western Digital Corp company, has been assigned a patent (11,049,568) developed by Yada, Shinsuke, Yokkaichi, Japan, for “three-dimensional memory device with depletion region position control and method of erasing same using gate induced leakage.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Gate-induced leakage current that is independent of a location of a physical p-n junction between a semiconductor channel and a source/drain region can be provided within a NAND string of a three-dimensional memory device by employing at least one leakage current control circuit that is activated during an erase operation. During the erase operation, an accumulation region and an inversion region can be formed between a vertically-neighboring pair of electrically conductive layers with a depletion region therebetween. The depletion region can generate and inject majority charge carriers into the semiconductor channel during the erase operation. The depletion region can be formed in the source region or in the drain region and may not overlap with a physical p-n junction. Thus, the charge injection location can be independent of the location of the physical p-n junction.”

The patent application was filed on March 27, 2020 (16/832,320).

Subthreshold voltage forming of selectors in crosspoint memory array
SanDisk Technologies LLC, Addison, TX, a Western Digital Corp company, has been assigned a patent (11,049,559) developed by Jeon, Yoocharn, Palo Alto, CA, for a “subthreshold voltage forming of selectors in a crosspoint memory array.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Apparatuses and techniques are described for forming of selectors in a memory device such as a crosspoint memory array. A threshold switching selector is in series with a resistance-switching memory cell in a storage node. Prior to a first switching operation in the array, a stimulus is applied to the storage node to transform the selectors from an initial state having an initial threshold voltage to an operating state having a lower, operating threshold voltage. The stimulus can include a signal having a voltage which does not exceed the operating threshold voltage. To limit peak current consumption, the stimulus can be applied to different subsets of the array, one subset at a time.”

The patent application was filed on June 11, 2020 (16/899,423).

Non-volatile memory interface
SanDisk Technologies LLC, Addison, TX, a Western Digital Corp company, has been assigned a patent (11,048,443) developed by Mittal, Sajal, Bhatia, Sneha, and Ghatawade, Vinayak, Bangalore, India, for a “non-volatile memory interface.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A circuit comprising a non-volatile memory array, an Input/Output (IO) circuit, a decoder circuit, a control circuit, and a read/write circuit. The non-volatile memory array couples to an address decoder that identifies a location within the non-volatile memory array for a storage command. The IO circuit couples to a decoder circuit through a control bus. The decoder circuit decodes a command address and storage command from a fixed length command sequence received by the IO circuit over the data bus. The decoder circuit may include a serial-in parallel out (SIPO) circuit for decoding and parallel operation. The control circuit couples to the IO and decoder circuits and generates control signals to execute decoded storage commands. The read/write circuit couples to the non-volatile memory array and the control circuit. The read/write circuit transfers data between the non-volatile memory array and the IO circuit in response to the storage commands.”

The patent application was filed on March 25, 2020 (16/830,128).

Three-dimensional memory including self-aligned dielectric isolation regions for connection via structures
SanDisk Technologies LLC, Addison, TX, a Western Digital Corp company, has been assigned a patent (11,043,455) developed by Kai, James, Santa Clara, CA, Alsmeier, Johann, San Jose, CA, and Yu, Jixin, Milpitas, CA, for “three-dimensional memory device including self-aligned dielectric isolation regions for connection via structures and method of making the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate. Memory stack structures are formed through the vertically alternating sequence. The vertically alternating sequence is divided into alternating stacks of insulating layers and sacrificial material layers by forming backside trenches therethrough. Each neighboring pair of alternating stacks is laterally spaced apart from each other by a respective backside trench. The sacrificial material layers are replaced with multipart layers. Each multipart layer includes a respective electrically conductive layer that laterally extends continuously between a respective neighboring pair of backside trenches and at least one dielectric material plate that is a remaining portion of a sacrificial material layer, is laterally enclosed by the respective electrically conductive layer, and is laterally spaced from a most proximal one of the backside trenches by a uniform lateral offset distance.”

The patent application was filed on July 23, 2019 (16/519,260).

Refresh operations for dedicated groups of blocks of memory cells
SanDisk Technologies LLC, Addison, TX, a Western Digital Corp company, has been assigned a patent (11,043,280) developed by Prakash, Abhijith, Milpitas, CA, and Yuan, Jiahui, Fremont, CA, for “refresh operations for dedicated groups of blocks of memory cells.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Apparatuses and techniques are described for periodically refreshing word line voltages in a group of blocks in a memory device. In one aspect, each group of blocks stores the same number of bits per cell. For example, one group of blocks can be reserved for single level cell (SLC) data and another group of blocks can be reserved for multi-level cell (MLC) data. A common refresh voltage signal can be applied to the blocks in a group, where the voltage signal is optimized based on the number of bits per cell stored by the memory cells of the group. For an SLC block, the refresh voltage signal can decrease a floating voltage of the word lines. For an MLC block, the refresh voltage signal can increase a floating voltage of the word lines.”

The patent application was filed on February 13, 2020 (16/790,306).

Sense amplifier architecture providing improved memory performance
SanDisk Technologies LLC, Addison, TX, a Western Digital Corp company, has been assigned a patent (11,043,276) developed by Yadala, Sridhar, Santoki, Kishan, and Samineni, Rangarao, Bangalore, India, for a “sense amplifier architecture providing improved memory performance.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A sense amplifier for a memory circuit is presented that can reduce sensing times by introduction of a local reference generator. The sense amplifier includes two capacitors that are pre-charged prior to a sensing operation. A first of the capacitors is connected so that it can discharge through a selected memory cell at a rate dependent on the conductivity of the selected memory cell. After a sensing interval in which the first capacitor can discharge through the selected memory cell, the voltage level on the first capacitor is compared with the voltage level on the second capacitor to determine the result of the sensing operation.”

The patent application was filed on February 20, 2020 (16/796,270).

Three-dimensional memory device having on-pitch drain select gate electrodes
SanDisk Technologies LLC, Addison, TX, a Western Digital Corp company, has been assigned a patent (11,037,943) developed by Imai, Muneyuki, Yokkaichi, Japan, and Kai, James, Santa Clara, CA, for “three-dimensional memory device having on-pitch drain select gate electrodes and method of making the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”An array of memory stack structures extends through an alternating stack of insulating layers and electrically conductive layers. The drain-select-level assemblies may be provided by forming drain-select-level openings through a drain-select-level sacrificial material layer, and by forming a combination of a cylindrical electrode portion and a first gate dielectric mayin each first drain-select-level opening while forming a second gate dielectric directly on a sidewall of each second drain-select-level opening in a second subset of the drain-select-level openings. A strip electrode portion is formed by replacing the drain-select-level sacrificial material layer with a conductive material. Structures filling the second subset of the drain-select-level openings may be used as dummy structures at a periphery of an array. The dummy structures are free of gate electrodes and thus prevents a leakage current therethrough.”

The patent application was filed on May 8, 2019 (16/406,283).

Bonded die assembly containing partially filled through-substrate via structures
SanDisk Technologies LLC, Addison, TX, a Western Digital Corp company, has been assigned a patent (11,037,908) developed by Wu, Chen, Leuven, Belgium, Rabkin, Peter, Cupertino, CA, Chen, Yangyin, Leuven, Belgium, and Higashitani, Masaaki, Cupertino, CA, for “bonded die assembly containing partially filled through-substrate via structures and methods for making the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A bonded assembly includes a first semiconductor die including a first substrate, first semiconductor devices located on the first substrate, first dielectric material layers located on the first semiconductor devices and embedding first metal interconnect structures, and first through-substrate via structures extending through the first substrate and contacting a respective first metal interconnect structure. Each of the first through-substrate via structures laterally surrounds a respective core cavity that contains a void or a dielectric fill material portion. The bonded assembly includes a second semiconductor die attached to the first semiconductor die, and including a second substrate, second semiconductor devices located on the second substrate, second dielectric material layers located on the second semiconductor devices and embedding second metal interconnect structures, and bonding pad structures electrically connected to a respective one of the second metal interconnect structures and bonded to a respective first through-substrate via structure.”

The patent application was filed on July 25, 2019 (16/521,849).

Temperature and cycling dependent refresh operation for memory cells
SanDisk Technologies LLC, Addison, TX, a Western Digital Corp company, has been assigned a patent (11,037,641) developed by Prakash, Abhijith, Shanthakumar, Vishwanath Basavaegowda, Milpitas, CA, and Yuan, Jiahui, Fremont, CA, for “temperature and cycling dependent refresh operation for memory cells.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Apparatuses and techniques are described for periodically refreshing word line voltages in a memory device. A decision to perform a refresh operation is made based on the temperature and number of program-erase (P-E) cycles. In one approach, the refresh operation is not performed if the number of P-E cycles is below a threshold number and/or the temperature is below a threshold temperature. When the temperature and number of P-E cycles indicate that a refresh operation should be performed, a timer counts an elapsed time until the elapsed time reaches an allowed discharge time. The allowed discharge time can be based on the temperature, number of P-E cycles, and other factors which affect an expected number of fail bits. The allowed discharge time can also change as the temperature changes during the counting of the elapsed time.”

The patent application was filed on December 5, 2019 (16/704,817).

Multi-pass programming process for memory device which omits verify test in first program pass
SanDisk Technologies LLC, Addison, TX, a Western Digital Corp company, has been assigned a patent (11,037,640) developed by Baraskar, Ashish, Santa Clara, CA, Lu, Ching-Huang, Fremont, CA, Diep, Vinh, San Jose, CA, and Dong, Yingda, Los Altos, CA, for a “multi-pass programming process for memory device which omits verify test in first program pass.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Techniques are provided to reduce neighbor word line interference and charge loss in a multi-pass program operation. In one implementation, the first pass of a multi-pass program operation uses one or more program pulses without performing associated verify tests. The memory cells may be programmed to different intermediate threshold voltage (Vth) distributions in the first program pass. Different bit line voltages can be used to obtain the different intermediate Vth distributions when the single program pulse is applied. In other cases, multiple program pulses are applied without performing verify tests. The intermediate Vth distributions can be provided for the memory cells assigned to the higher data states but not the lower data states, or for memory cells assigned to both the higher and lower data states.”

The patent application was filed on June 12, 2020 (16/900,015).

Power management for multi-plane read operations
SanDisk Technologies LLC, Addison, TX, a Western Digital Corp company, has been assigned a patent (11,037,635) developed by Lien, Yu-Chung, San Jose, CA, Eliash, Tomer, Kfar Saba, Israel, and Tseng, Huai-Yuan, San Ramon, CA, for a “power management for multi-plane read operations.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Apparatuses and techniques are described for managing power consumption in a memory device. When a multi-plane read command is received, a control circuit determines whether the blocks identified by the read command are fully or partially programmed. If they are fully programmed, the read command is executed while applying a common read pass voltage to the unprogrammed word lines of the respective blocks. If the blocks are not all fully programmed, the control circuit determines a last-programmed word line. If the last-programmed word lines are not equal in each block, the read command is executed while applying a base read pass voltage to the unprogrammed word lines of one or more higher-programmed blocks and a lower read pass voltage to the unprogrammed word lines of one or more lower-programmed blocks.”

The patent application was filed on February 6, 2020 (16/784,171).

Column erasing in non-volatile memory strings
SanDisk Technologies LLC, Addison, TX, a Western Digital Corp company, has been assigned a patent (11,037,631) developed by Pachamuthu, Jayavel, San Jose, CA, Desai, Amul Dhirajbhai, Milpitas, CA, and Babariya, Ankitkumar, San Jose, CA, for a “column erasing in non-volatile memory strings.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Strings of non-volatile memory cells include one or more joint regions adjacent to dummy non-volatile memory cells. During erase operations, different voltage levels are used for different dummy word lines coupled to respective dummy non-volatile memory cells. For example, a selection circuit may set a voltage level of a particular dummy word line to a voltage level greater than a different dummy word line. In another example, the selection circuit may determine a voltage level for a given dummy word line based on a distance between a non-volatile memory cell coupled to the given dummy word line and a selection device included in a string of non-volatile memory cells. Electron holes generated using the dummy word lines during erase operations may neutralize undesired trapped charges in a non-volatile memory string, thereby reducing disparity in erase times for different strings in the non-volatile memory circuit.”

The patent application was filed on January 18, 2019 (16/252,300).

Semiconductor package and fabricating semiconductor package
SanDisk Information Technology,(Shanghai) Co., Ltd., Shanghai, China, a Western Digital Corp company, has been assigned a patent (11,031,371) developed by Chiu, Chin Tien, Taichung, Taiwan, Tai, Tiger, Qian, Ken, Shanghai, China, Liao, C C, Changhua, Taiwan, Takiar, Hem, and Singh, Gursharan, Fremont, CA, for “semiconductor package and method of fabricating semiconductor package.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”The present technology relates to a semiconductor package. The semiconductor package comprises: a first component comprising a plurality of first dies stacked on top of each other, each of first dies comprising at least one side surface and an electrical contact exposed on the side surface, and the plurality of first dies aligned so that the corresponding side surfaces of all first dies substantially coplanar with respect to each other to form a common sidewall, a first conductive pattern formed over the sidewall and at least partially spaced away from the sidewall, the first conductive pattern electrically interconnecting the electrical contacts of the plurality of first dies, at least one second component, and a second conductive pattern formed on a surface of the second component, the second conductive pattern affixed and electrically connected to the first conductive pattern formed over the sidewall of the first component.”

The patent application was filed on September 14, 2017 (15/704,984).

Connectivity detection for wafer-to-wafer alignment and bonding
SanDisk Technologies LLC, Addison, TX, a Western Digital Corp company, has been assigned a patent (11,031,308) developed by Lee, Seungpil, San Ramon, CA, and Kim, Kwang-Ho, Pleasanton, CA, for “connectivity detection for wafer-to-wafer alignment and bonding.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A first workpiece includes first active pads, a first test pad, and a second test pad on a primary surface of the first workpiece, the first test pad electrically connected to the second test pad. A second workpiece includes second active pads, a third test pad, and a fourth test pad on a primary surface of the second workpiece. The first and second workpieces are bonded along an interface between the primary surface of the first workpiece and the primary surface of the second workpiece to bond the first active pads with the second active pads, bond the first test pad with the third test pad, and bond the second test pad with the fourth test pad. Connectivity detection circuits test electrical connectivity between the third test pad and the fourth test pad.”

The patent application was filed on May 30, 2019 (16/426,984).

Hot-cold VTH mismatch using VREAD modulation
SanDisk Technologies LLC, Addison, TX, a Western Digital Corp company, has been assigned a patent (11,031,088) developed by Kang, Dae Wung, Los Gatos, CA, Rabkin, Peter, and Higashitani, Masaaki, Cupertino, CA, for a “hot-cold VTH mismatch using VREAD modulation.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Methods and systems for improving the reliability of data stored within a semiconductor memory over a wide range of operating temperatures are described. The amount of shifting in the threshold voltages of memory cell transistors over temperature may depend on the location of the memory cell transistors within a NAND string. To compensate for these variations, the threshold voltages of memory cell transistors in the middle of the NAND string or associated with a range of word lines between the ends of the NAND string may be adjusted by increasing the word line voltages biasing memory cell transistors on the drain-side of the selected word line when the read temperature is greater than a first threshold temperature and/or decreasing the word line voltages biasing memory cell transistors on the source-side of the selected word line when the read temperature is less than a second threshold temperature.”

The patent application was filed on June 23, 2020 (16/909,830).

Non-volatile memory with fast partial page operation
SanDisk Technologies LLC, Addison, TX, a Western Digital Corp company, has been assigned a patent (11,031,085) developed by Dunga, Mohan V, Santa Clara, CA, and Shukla, Pitamber, Milpitas, CA, for a “non-volatile memory with fast partial page operation.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The memory structure includes one or more planes of non-volatile memory cells. Each plane is divided into a plurality of partial planes. The control circuit is configured to write to and read from the memory cells by writing a partial page into a particular partial plane and reading the partial page from the particular partial plane using a set of parameters optimized for the particular partial plane.”

The patent application was filed on June 9, 2020 (16/896,960).

Magnetic random-access memory with selector voltage compensation
SanDisk Technologies LLC, Addison, TX, a Western Digital Corp company, has been assigned a patent (11,031,059) developed by Petti, Christopher J., Mountain View, CA, Liu, Tz-Yi, Palo Alto, CA, Al-Shamma, Ali, San Jose, CA, and Jeon, Yoocharn, Palo Alto, CA, for a “magnetic random-access memory with selector voltage compensation.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Magnetic random-access memory (MRAM) circuits are provided herein. In one example implementation, an MRAM circuit includes control circuitry coupled to a magnetic tunnel junction (MTJ) element in series with a selector element. This control circuitry is configured to adjust current through the selector element when the selector element is in a conductive state. The circuit also includes a compensation circuitry configured to compensate for a offset voltage across the selector element in the conductive state based on adjustments to the current through the selector element. An output circuit is also configured to report a magnetization state of the MTJ element.”

The patent application was filed on February 21, 2019 (16/281,699).

Key-value store with partial data access
SanDisk Technologies LLC, Addison, TX, a Western Digital Corp company, has been assigned a patent (11,030,156) developed by Cheru, Tomy, Thrissur, India, O’Krafka, Brian, Austin, TX, Samuels, Allen, San Jose, CA, and Krishnan, Manavalan, Fremont, CA, for a “key-value store with partial data access.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Apparatuses, systems, methods, and computer program products are disclosed for key-value stores with partial data access. An interface module is configured to receive a data object for storage in a key-value store. The data object may include a key and a value. A block object module is configured to generate a plurality of block objects smaller than the data object. A block object may include a new key and a new value. The new key may be based on the key for the data object and on metadata for the new value. The new value may be based on at least a portion of the value for the data object. A storage module is configured to store the block objects in the key-value store.”

The patent application was filed on August 9, 2016 (15/232,789).