Samsung Electronics Assigned Twenty-Six Patents

Storage for performing map scheduling
Samsung Electronics Co., Ltd., Suwon-si, Korea, has been assigned a patent (11,016,904) developed by Cho, Yongwon, Suwon-si, Korea, Kim, Hyeonwu, Gyeongsangbuk-do, Korea, and Ahn, Seok-Won, Suwon-si, Korea, for “storage device for performing map scheduling and electronic device including the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A storage device includes a controller and a memory. In response to a request of a host, the controller generates: (A) a first list as a result of counting: (1) the number of first page numbers included in a first range among page numbers included in a logical address received from the host and (2) the number of second page numbers included in a second range not overlapping the first range, (B) generates a second list as a result of respectively grouping the first page numbers and the second page numbers based on the first list, and (C) translates the logical address to a physical address based on the second list and the first map data. The memory stores the first map data to be provided to the controller. The first map data matches the first page numbers and the second page numbers with respective physical addresses.”

The patent application was filed on August 17, 2019 (Appl. No.16/543,531).

Storage using host memory and operating
Samsung Electronics Co., Ltd., Suwon-si, Korea, has been assigned a patent (11,016,846) developed by Eom, Kicheol, Sim, Jaeho, Seoul, Korea, Lee, Dong-Ryoul, Incheon, Korea, Yi, Hyun Ju, Hwseong-si, Korea, and Leem, Hyotaek, Hwaseong-si, Korea, for “storage device using host memory and operating method thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A storage device sharing a host memory of a host, the storage device includes a serial interface that exchanges data with the host, and a storage controller that stores buffering data in a host memory buffer allocated by the host through the serial interface. The storage controller performs error correction encoding and error correction decoding on the buffering data.”

The patent application was filed on August 7, 2019 (Appl. No.16/533,894).

Storage system
Samsung Electronics Co., Ltd., Suwon-si, Korea, has been assigned a patent (11,016,689) developed by Yu, Geun Yeong, Shin, Beom Kyu, Seongnam-si, Korea, Lee, Myung Kyu, Seoul, Korea, Kong, Jun Jin, Yongin-si, Korea, and Son, Hong Rak, Anyang-si, Korea, for a “data storage system.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data storage system that provides improved reliability and performance comprises a first memory device including a plurality of first storage components and a first memory controller, the first memory controller controls operation of the first storage components, a second memory device including a plurality of second storage components and a second memory controller, the second memory controller controls operation of the second storage components, a grading device determining grades for each of the first storage components and the second storage components, and a system controller that the location of data based on the grades of the first storage components and the second storage components.”

The patent application was filed on September 6, 2017 (Appl. No.15/696,443).

Storage device that uses host memory buffer and memory management
Samsung Electronics Co., Ltd., Suwon-si, Korea, has been assigned a patent (11,011,243) developed by Lee, Dong-Ryoul, Incheon, Korea, Yi, Hyun Ju, Hwaseong-si, Korea, Sim, Jaeho, Eom, Kicheol, Seoul, Korea, and Leem, Hyotaek, Hwaseong-si, Korea, for a “storage device that uses a host memory buffer and a memory management method including the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A storage device is provided which shares a host memory with a host. The storage device includes an interface that exchanges data with the host and implements a protocol to use a partial area of the host memory as a buffer of the storage device. A storage controller of the storage device monitors deterioration information of a first area of the buffer and transmits a corruption prediction notification associated with the first area to the host based on a result of the monitoring.”

The patent application was filed on August 13, 2019 (Appl. No.16/539,729).

Supporting machine learning algorithms and data pattern matching in ethernet SSD
Samsung Electronics Co., Ltd., Suwon-si, Korea, has been assigned a patent (11,010,431) developed by Olarig, Sompong P., Pleasanton, CA, Worley, Fred, San Jose, CA, and Farahpour, Nazanin, Los Angeles, CA, for “method and apparatus for supporting machine learning algorithms and data pattern matching in ethernet SSD.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data storage device includes a memory array for storing data, a host interface for providing an interface with a host computer running an application, a central control unit configured to receive a command in a submission queue from the application and initiate a search process in response to a search query command, a preprocessor configured to reformat data contained in the search query command and generate a reformatted data, and one or more data processing units configured to extract one or more features from the reformatted data and perform a data operation on the data stored in the memory array in response to the search query command and return matching data from the data stored in the memory array to the application via the host interface.”

The patent application was filed on March 28, 2017 (Appl. No.15/472,061).

Memory for adjusting memory capacity per channel
Samsung Electronics Co., Ltd., Suwon-si, Korea, has been assigned a patent (11,010,316) developed by Park, Jae-Won, Hwaseong-si, Korea, Ryu, Je-Min, Seoul, Korea, Shin, Sang-Hoon, Yongin-si, Korea, and Jung, Jae-Hoon, Seoul, Korea, for “memory device for adjusting memory capacity per channel and memory system including the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory device includes a first channel including a first cell array and communicating with a memory controller through a first path, a second channel including a second cell array and communicating with the memory controller through a second path, and an assignment control circuit configured to monitor memory usage of the first and second channels and further assign a storage space of a portion of the second cell array to the first channel when the memory usage of the first cell array exceeds a threshold value. Access to the storage space of the portion of the second cell array assigned to the first channel is performed through the first path.”

The patent application was filed on August 28, 2018 (Appl. No.16/115,089).

Storage device including nonvolatile memory
Samsung Electronics Co., Ltd., Suwon-si, Korea, has been assigned a patent (11,004,517) developed by Lee, Yunjung, Suwon-si, Korea, Kim, Chanha, Kang, Suk-eun, Hwaseong-si, Korea, Ro, Seungkyung, Anyang-si, Korea, Lee, Kwangwoo, Seoul, Korea, Lee, Juwon, Hwaseong-si, Korea, Lee, Jinwook, and Lee, Heewon, Seoul, Korea, for a “storage device including nonvolatile memory device and operating method thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A storage device includes a nonvolatile memory device including a memory block and a memory controller. The memory block includes a first memory region connected with a first word line and a second memory region connected with a second word line. The memory controller sets a read block voltage based on a first read voltage of the first memory region. The memory controller determines a second read voltage of the second memory region based on variation information and the read block voltage.”

The patent application was filed on March 18, 2019 (Appl. No.16/356,182).

Multi-protocol IO infrastructure for flexible storage platform
Samsung Electronics Co., Ltd., Suwon-si, Korea, has been assigned a patent (11,003,609) developed by Worley, Fred, Rogers, Harry, Krishnan, Sreenivas, Ping, Zhan, San Jose, CA, and Scriber, Michael, Hayward, CA, for a “multi-protocol IO infrastructure for a flexible storage platform.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A flexible storage system. A storage motherboard accommodates, on a suitable connector, a storage adapter circuit that provides protocol translation between a host bus interface and a storage interface, and that provides routing, to accommodate a plurality of mass storage devices that may be connected to the storage adapter circuit through the storage motherboard. The storage adapter circuit may be replaced with a circuit supporting a different host interface or a different storage interface.”

The patent application was filed on August 14, 2020 (Appl. No.16/994,405).

Non-volatile memory storage capable of self-reporting performance capabilities
Samsung Electronics Co., Ltd., Suwon-si, Korea, has been assigned a patent (11,003,381) developed by Marripudi, Gunneswara R., Fremont, CA, and Maram, Vishwanath, San Jose, CA, for a “non-volatile memory storage device capable of self-reporting performance capabilities.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Provided is a storage device including a first non-volatile storage media having first performance capabilities, a second non-volatile storage media having second performance capabilities different from the first performance capabilities, and a device controller configured to report to a host software the first performance capabilities, the second performance capabilities, changes to the first performance capabilities, and changes to the second performance capabilities.”

The patent application was filed on May 5, 2017 (Appl. No.15/588,567).

Cost-effective solid state disk data protection for hot removal event
Samsung Electronics Co., Ltd., Suwon-si, Korea, has been assigned a patent (11,003,229) developed by Olarig, Sompong Paul, Pleasanton, CA, Kachare, Ramdas P, Cupertino, CA, and Wu, Wentao, Milpitas, CA, for a “cost-effective solid state disk data protection method for hot removal event.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A system is disclosed that provides emergency backup power to a solid-state drive (SSD) that may not contain any internal supercapacitors. The SSD may include a first connector and a hold-up power supply. The first connector may have a predetermined form factor and may being capable of being connected to a corresponding connector of a midplane of a storage system. The first connector may include a main power connection that is connected to a main power supply of the midplane if the first connector is connected to the corresponding connector of the midplane. The hold-up power supply may be internal to the SSD, and may receive hold-up energy from an external energy source for a predetermined amount of time after the first connector has been disconnected from the main power connection of the midplane so that the SSD may store any host data write requests that the SSD has acknowledged.”

The patent application was filed on August 23, 2018 (Appl. No.16/111,167).

Memory and method of operating
Samsung Electronics Co., Ltd., Suwon-si, Korea, has been assigned a patent (10,998,038) developed by Kim, Jongryul, Dangjin-si, Korea, Na, Taehui, Seoul, Korea, Kim, Dueung, Yongin-si, Korea, and Baek, Jongmin, Hwaseong-si, Korea, for “memory device and method of operating the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory device includes a plurality of memory cells each including a switching device and a storage device having a phase change material, a decoder circuit including a first bias circuit inputting a first bias voltage to a selected word line connected to a selected memory cell, a second bias circuit inputting a second bias voltage to a selected bit line, a first selection switching device and a first non-selection switching device connected between the first bias circuit and the selected word line, and a second selection switching device and a second non-selection switching device connected between an adjacent word line and the first bias circuit, a control logic sequentially turning off the first selection switching device and the second non-selection switching device, and a sense amplifier comparing a voltage of the selected word line with a reference voltage to determine data of a read operation.”

The patent application was filed on February 21, 2020 (Appl. No.16/797,700).

Storage devices that support cached physical address verification
Samsung Electronics Co., Ltd., Suwon-si, Korea, has been assigned a patent (10,997,066) developed by Kim, Dong-Woo, Suwon-si, Korea, No, Jae Sun, Anyang-si, Korea, Yoon, Song Ho, Yongin-si, Korea, Lee, Kyoung Back, Hwaseong-si, Korea, and Jeong, Wook Han, Pocheon-si, Korea, for “storage devices that support cached physical address verification and methods of operating same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A storage device includes a descramble module configured to descramble at least a portion of a read command, which includes logical block address (LBA) information and first meta information, into first signature information and first physical address (PA) information, for accessing a flash memory. A compare module is provided, which is configured to compare the first signature information against stored signature information to thereby determine an equivalency or discrepancy therebetween. An access module is provided, which is configured to use the first PA information to access a data region of the flash memory, upon determination of the equivalency by said compare module.”

The patent application was filed on September 18, 2018 (Appl. No.16/133,778).

Data center storage evaluation framework simulation
Samsung Electronics Co., Ltd., Suwon-si, Korea, has been assigned a patent (10,996,970) developed by Hoseinzadeh, Morteza, La Jolla, CA, Yang, Zhengyu, Malden, MA, Wong, Terence Ping, San Diego, CA, and Evans, David, San Marcos, CA, for a “method for data center storage evaluation framework simulation.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”An a method for simulating a data center is provided and a non-transitory computer-readable storage medium having recorded thereon a computer program for executing the method of simulating a data center. The method includes storing at least one hardware configuration file and at least one functional description file of a data center to be simulated in a configuration file application, generating a simulation program of the data center using the at least one hardware configuration file and the at least one functional description file by a data center storage evaluation framework (DCEF) application, and executing a flow-based simulation on the simulation program generated by the DCEF application by a simulator.”

The patent application was filed on February 14, 2018 (Appl. No.15/896,590).

Configuring NVMe-oF devices using baseboard management controller (BMC)
Samsung Electronics Co., Ltd., Suwon-si, Korea, has been assigned a patent (10,996,899) developed by Olarig, Sompong Paul, Pleasanton, CA, Pham, Son T., San Ramon, CA, and Kachare, Ramdas, Cupertino, CA, for “system and method of configuring NVMe-oF devices using a baseboard management controller (BMC).“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Disclosed herein is a computer storage array providing one or more remote initiators with NVMe over Fabrics (NVMe-oF) access to one or more storage devices connected to the storage array. According to an example embodiment, the computer storage array comprises: a computer processor configured to run an operating system for managing networking protocols, a network switch configured to establish an NVMe-oF connection and route data between the initiators and the storage devices, a baseboard management controller (BMC) configured to configure a network setting or NVMe-oF setting of the storage devices, a PCIe switch connecting the BMC with each of the storage devices via a PCIe bus, and a computer motherboard including the PCIe bus and to which the computer processor, network switch, BMC and PCIe switch are installed.”

The patent application was filed on August 14, 2019 (Appl. No.16/540,989).

Storage including host device and storage device configured to perform selective purge operation
Samsung Electronics Co., Ltd., Suwon-si, Korea, has been assigned a patent (10,996,883) developed by Kim, Dong-Min, Hwaseong-si, Korea, and Yoon, Songho, Yongin-si, Korea, for a “storage system including host device and storage device configured to perform selective purge operation.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A storage system includes a host device and a storage device. The host device generates a write command, a logical address of write data corresponding to the write command, and a selective purge tag indicating that the write data are targeted for selective purge. The storage device receives the write command, the logical address, and the selective purge tag, stores write data, and logically erases the stored write data upon receiving an erase command from the host device. In addition, the storage device physically erases the stored write data upon receiving a selective purge request from the host device.”

The patent application was filed on May 21, 2018 (Appl. No.15/984,446).

Storage device and method for operating
Samsung Electronics Co., Ltd., Suwon-si, Korea, has been assigned a patent (10,991,412) developed by Jung, Sang Won, Busan, Korea, Oh, Shin Ho, Yongin-si, Korea, and Ham, Dong Hoon, Suwon-si, Korea, for “storage device and method for operating storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A storage device may include a monitoring module which monitors a characteristic degradation rate of a plurality of blocks included in a cell array of a nonvolatile memory, a group management module which designates the plurality of blocks as one or more groups, on the basis of a monitoring result of the monitoring module, a refresh period management module which determines refresh periods for each of the one or more groups, and a processor which performs refresh on the one or more groups in accordance with the determined refresh periods.”

The patent application was filed on September 24, 2020 (Appl. No.17/030,766).

Identify FPGA and SSD pairing in multi-device environment
Samsung Electronics Co., Ltd., Suwon-si, Korea, has been assigned a patent (10,990,554) developed by Pinto, Oscar P., San Jose, CA, and Kachare, Ramdas P., Pleasanton, CA, for a “mechanism to identify FPGA and SSD pairing in a multi-device environment.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A system is disclosed. The system may include a Solid State Drive (SSD) and a co-processor. The SSD may include storage for data, storage for a unique SSD identifier (ID) and storage for a unique co-processor ID. The co-processor include storage for the unique SSD ID, and storage for the unique co-processor ID. A hardware interface may permit communication between the SSD and the co-processor.”

The patent application was filed on June 7, 2019 (Appl. No.16/435,442).

Memory controller, operating method and storage device
Samsung Electronics Co., Ltd., Suwon-si, Korea, has been assigned a patent (10,990,536) developed by Kim, Jung-Hoon, Yongin-si, Korea, and Lee, Young-Sik, Seoul, Korea, for “memory controller, operating method of the memory controller, and storage device including the memory controller.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory controller, an operating method of the memory controller, and a storage device including the memory controller are disclosed. The memory controller includes: a memory configured to store an address mapping table and a segment mapping table, and a mapping data management module configured to select at least two updated segments among a plurality of segments included in the address mapping table as page data to be stored in one page of a nonvolatile memory, wherein each of the plurality of segments includes a plurality of mapping entries representing mapping information between logical addresses and physical addresses, and wherein the segment mapping table includes physical addresses representing areas in which each of the plurality of segments is stored in the nonvolatile memory.”

The patent application was filed on July 9, 2019 (Appl. No.16/506,308).

Storage using host memory buffer
Samsung Electronics Co., Ltd., Suwon-si, Korea, has been assigned a patent (10,983,722) developed by Kim, Hyun-Seok, and Jun, Walter, Seoul, Korea, for a “data storage device using host memory buffer and method of operating the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data storage device includes a nonvolatile memory device, a storage controller and a mapping controller. The nonvolatile memory device stores an execution code that controls operations of the data storage device. The storage controller uploads and stores the execution code from the nonvolatile memory device to a host memory buffer included in an external host device, and downloads the execution code in realtime from the host memory buffer to execute the execution code that is downloaded from the host memory buffer. The mapping controller manages a mapping table including mapping relations between the execution code and host addresses of the host memory buffer at which the execution code is stored. A speed of accessing the execution code is increased and performance of the data storage device is enhanced by using the host memory buffer as storage of the execution code to control the operation of the data storage device.”

The patent application was filed on July 9, 2019 (Appl. No.16/506,613).

Storage devices and methods for manufacturing
Samsung Electronics Co., Ltd., Suwon-si, Korea, has been assigned a patent (10,978,638) developed by Park, Jongchul, and Kim, Sang-Kuk, Seongnam-si, Korea, for “data storage devices and methods for manufacturing the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A method of manufacturing a data storage device may include forming a magnetic tunnel junction layer on a substrate, irradiating a first ion beam on the magnetic tunnel junction layer to form magnetic tunnel junction patterns separated from each other, irradiating a second ion beam on the magnetic tunnel junction layer, and irradiating a third ion beam on the magnetic tunnel junction layer. The first ion beam may be irradiated at a first incident angle. The second ion beam may be irradiated at a second incident angle that may be smaller than the first incident angle. The third ion beam may be irradiated to form sidewall insulating patterns on sidewalls of the magnetic tunnel junction patterns based on re-depositing materials separated by the third ion beam on the sidewalls of the magnetic tunnel junction patterns.”

The patent application was filed on April 1, 2020 (Appl. No.16/837,424).

Three-dimensional semiconductor memory
Samsung Electronics Co., Ltd., Suwon-si, Korea, has been assigned a patent (10,978,479) developed by Lee, Changhyun, Son, Byoungkeun, Suwon-si, Korea, and Cho, Hyejin, Anyang-si, Korea, for “three-dimensional semiconductor memory devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells on the substrate includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region. The gate dielectric layers may include a composite of a tunnel insulating layer, a charge storage layer, a relatively high bandgap barrier dielectric layer and a blocking insulating layer having a relatively high dielectric strength.”

The patent application was filed on February 28, 2020 (Appl. No.16/804,982).

Three-dimensional semiconductor having memory block and separation structures
Samsung Electronics Co., Ltd., Suwon-si, Korea, has been assigned a patent (10,978,465) developed by Lee, Byoung Il, Seoul, Korea, Seo, Yu Jin, Daejeon, Korea, and Jin, Jun Eon, Suwon-si, Korea, for a “three-dimensional semiconductor device having a memory block and separation structures.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A three-dimensional semiconductor device includes first and second extended regions disposed on a substrate spaced apart from each other, a memory block disposed on the substrate between the first and second extended regions, and first and second main separation structures disposed on the substrate spaced apart from each other. The first extended region, the memory block and the second extended region are disposed between the first and second main separation structures. The memory block includes data storage regions and word lines. The word lines extend from the memory block and pass through the first and second extended regions. A distance between the first and second main separation structures located on both sides of the first extended region is greater than a distance between the first and second main separation structures located on both sides of the memory block.”

The patent application was filed on December 20, 2018 (Appl. No.16/227,985).

Page buffer and memory
Samsung Electronics Co., Ltd., Suwon-si, Korea, has been assigned a patent (10,978,113) developed by Chun, Jinyoung, Seoul, Korea, for “page buffer and memory device including the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A page buffer includes a charging circuit, first and second storage circuits, and a selection circuit. The charging circuit charges a bit line during a precharging period. The first storage circuit determines and stores data corresponding to a state of a selected memory cell among memory cells connected to the bit line while the charging circuit charges the bit line. The second storage circuit, which is a circuit separate from the first storage circuit, determines and stores data corresponding to a state of the selected memory cell after the precharging period. The selection circuit outputs a control voltage controlling a switch element connected between the bit line and the charging circuit, and determines a magnitude of the control voltage during the precharging period, based on the data stored in the first storage circuit.”

The patent application was filed on January 9, 2020 (Appl. No.16/738,598).

Storage device, system and method
Samsung Electronics Co., Ltd., Suwon-si, Korea, has been assigned a patent (10,976,933) developed by Lee, Young-min, Seo, Sung-ho, Seoul, Korea, Oh, Hwa-seok, Yongin-si, Korea, Yoo, Kyung-phil, and Jang, Seong-yong, Seoul, Korea, for “storage device, storage system and method of operating the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Provided are a storage device, a storage system, and a method of operating the same. A storage device communicably connected to a host may include a non-volatile memory configured to store at least one piece of boot data necessary for booting the storage device, and a device controller configured to receive an interface initialize command (IFIC) from the host, predict requested boot data requested by the host from among the at least one piece of boot data based on the IFIC, and control the non-volatile memory to read the requested boot data.”

The patent application was filed on January 3, 2018 (Appl. No.15/860,756).

Computing system with nonvolatile storage and operating
Samsung Electronics Co., Ltd., Suwon-si, Korea, has been assigned a patent (10,970,235) developed by Hong, JuHyung, Yongin-si, Korea, and Chung, Eui-Young, Seoul, Korea, for “computing system with a nonvolatile storage and operating method thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”An operating method of a computing system includes storing, in a submission queue, a command entry corresponding to a request for one of input and output, fetching the command entry from the submission queue, moving data corresponding to the request within a host memory that is under control of a storage device, after moving the data, updating a completion status of the request in a completion queue, and after updating the completion queue, transferring the data between the host memory and the storage device.”

The patent application was filed on September 19, 2017 (Appl. No.15/709,112).

Storage device and operating
Samsung Electronics Co., Ltd., Suwon-si, Korea, has been assigned a patent (10,970,164) developed by Lee, Chulseung, Seoul, Korea, Hwang, Soon Suk, Ansan-si, Korea, and Lee, Choongeui, Suwon-si, Korea, for “storage device and operating method of storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A storage device includes a nonvolatile memory device, and a controller that reads first data from the nonvolatile memory device. When a number of first errors of the first data is not smaller than a first threshold value, the controller determines whether the first errors include timing errors arising from a variation of signal transmission timings between the nonvolatile memory device and the controller and performs a retraining operation on the signal transmission timings when the first errors include the timing errors.”

The patent application was filed on January 15, 2019 (Appl. No.16/248,540).