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Kioxia Assigned Twenty Patents

Semiconductor memory, method of manufacturing, semiconductor storage device, memory, packet protection circuit, and CRC calculation, reading of start-up information from different memory regions of memory, Pattern forming and of manufacturing semiconductor, nonvolatile semiconductor memory, semiconductor memory device with erase control, dicing method and laser processing

Semiconductor memory
Kioxia Corporation, Minato-ku, Japan, has been assigned a patent (11,056,152) developed by Tanaka, Takuto, Mori, Takeo, Terada, Takashi, and Tsuchiya, Takamichi, Yokkaichi, Japan, for a semiconductor memory device.

The abstract of the patent published by the U.S. Patent and Trademark Office states: According to one embodiment, a semiconductor memory device includes: a memory cell array including: a plurality of memory cells stacked above a substrate, and a plurality of word lines respectively coupled to gates of the plurality of memory cells and extending in a first direction, and a first film including a first area above the memory cell array and a second area different from the first area, and having a compressive stress higher than silicon oxide. In the first area, a plurality of first trenches extending in the first direction are aligned in a second direction that intersects the first direction. In the second area, a second trench in a mesh form is provided.

The patent application was filed on February 24, 2020 (16/798,524).

Semiconductor memory
Kioxia Corporation, Minato-ku, Japan, has been assigned a patent (11,049,877) developed by Oike, Go, Mie Mie, Japan, for a semiconductor memory.

The abstract of the patent published by the U.S. Patent and Trademark Office states: A semiconductor memory includes a substrate and an alternating stack of first insulators and first conductors above the substrate. First to third regions are provided in this order along a direction parallel to a surface of the substrate. The alternating stack is in a dummy region at part of each of the first to third regions. Second and third conductors extend in parallel to each other in the direction above a top one of the first conductors. A plurality of first pillars extend through the second conductor. A plurality of second pillars extend through the third conductor. A columnar first contact is provided on the second conductor in the first region, and a columnar second contact is provided on the third conductor in the first region. The second and third conductors are separated from each other in the first and second regions, and connected to each other in the third region.

The patent application was filed on June 8, 2020 (16/895,206).

Semiconductor memory and method of manufacturing
Kioxia Corporation, Minato-ku, Japan, has been assigned a patent (11,049,875) developed by Hazue, Shunsuke, Yokkaichi, Japan, for semiconductor memory device and method of manufacturing the same.

The abstract of the patent published by the U.S. Patent and Trademark Office states: A semiconductor memory device according to embodiments described herein, includes a first stacked body, a second stacked body, a first memory hole, a second memory hole, and a joint. In the first stacked body, a plurality of first conductive layers and a plurality of first insulating layers are alternately stacked. The second stacked body is disposed above the first stacked body, and a plurality of second conductive layers and a plurality of second insulating layers are alternately stacked therein. The first memory hole extends in the first stacked body in a first direction that is a stacking direction of the first stacked body. The second memory hole extends in the second stacked body in the first direction. The joint communicates the first memory hole and the second memory hole. The joint includes an inner wall surface and a sidewall insulating layer. The inner wall surface has a plane continuous with the inner wall of the first memory hole. The sidewall insulating layer is disposed on the inner wall surface of the joint.

The patent application was filed on March 12, 2020 (16/816,380).

Semiconductor storage device
Kioxia Corporation, Minato-ku, Japan, has been assigned a patent (11,049,573) developed by Funatsuki, Rieko, Yokohama Kanagawa, Japan, Maeda, Takashi, Kamakura Kanagawa, Japan, Shiga, Hidehiro, Yokohama Kanagawa, Japan, and Maejima, Hiroshi, Setagaya Tokyo, Japan, for a semiconductor storage device.

The abstract of the patent published by the U.S. Patent and Trademark Office states: A semiconductor storage device includes a first memory cell and a second memory cell which are connected to each other in series, a first word line which is connected to the first memory cell, a second word line which is connected to the second memory cell, and a control circuit. The control circuit is configured to charge a first node while applying a second voltage to the second word line and a first voltage to the first word line, to charge a second node on the basis of a voltage of the charged first node, to discharge the second node while applying the second voltage to the second word line and a third voltage to the first word line, and to read data from the first memory cell on the basis of voltages of the charged and discharged second node.

The patent application was filed on February 26, 2020 (16/802,471).

Memory, packet protection circuit, and CRC calculation
Kioxia Corporation, Minato-ku, Japan, has been assigned a patent (11,043,964) developed by Miyamoto, Yukimasa, Taki, Daisuke, Kanagawa, Japan, Kumagaya, Takeshi, and Horiguchi, Tomoya, Tokyo, Japan, for memory system, packet protection circuit, and CRC calculation method.

The abstract of the patent published by the U.S. Patent and Trademark Office states: A memory system includes a packet protection circuit. The packet protection circuit includes a plurality of first CRC calculation circuits, each configured to calculate a CRC of M-byte data, where M is an integer greater than or equal to 1 and less than N, where N is an integer greater than or equal to 2, a first selector configured to output a CRC calculation result of one of the first CRC calculation circuits, and a second CRC calculation circuit configured to calculate a CRC of L-byte data, where L<N, where L=N.times.Z, and Z is an integer greater than 1, and add the CRC of L-byte data to the CRC calculation result output from the first selector to generate a first CRC that is compared with a second CRC to detect an error in a data packet transmitted between the host interface unit and the host device.

The patent application was filed on February 28, 2020 (16/805,098).

Reading of start-up information from different memory regions of memory system
Kioxia Corporation, Minato-ku, Japan, has been assigned a patent (11,042,310) developed by Suzuki, Riki, Hida, Toshikatsu, Amaki, Takehiko, and Igahara, Shunichi, Kanagawa, Japan, for reading of start-up information from different memory regions of a memory system.

The abstract of the patent published by the U.S. Patent and Trademark Office states: A memory system includes a nonvolatile semiconductor memory including a first memory region for storing start-up information and a second memory region for storing a copy of the start-up information, a volatile semiconductor memory, and a controller. The controller is configured to determine whether or not an address of the second memory region is stored in the volatile semiconductor memory, issue a first start-up read command, which designates no read address, to the nonvolatile semiconductor memory to read the start-up information from the first memory region if the address of the second memory region is not stored in the volatile semiconductor memory, and issue a second start-up read command, which designates the address of the second memory region as a read address, to read the start-up information from the second memory region if the address of the second memory region is stored in the volatile semiconductor memory.

The patent application was filed on July 9, 2019 (16/506,475).

Memory system
Kioxia Corporation, Minato-ku, Japan, has been assigned a patent (11,025,281) developed by Kifune, Naoko, Yokohama and Uchikawa, Hironori, Fujisawa Kanagawa, Japan, for a memory system.

The abstract of the patent published by the U.S. Patent and Trademark Office states: A memory system includes a nonvolatile memory and a memory controller that encodes first XOR data generated by performing an exclusive OR operation on pieces of user data, wherein a value of each bit of the XOR data is generated by performing an exclusive OR operation on values of bits that are at one of a plurality of bit positions of a piece of user data, generates codewords by encoding the plurality of pieces of user data and the generated XOR data, respectively, and stores the codewords in the nonvolatile memory. The memory controller also performs a read operation by reading the codewords from the nonvolatile memory and decoding them. When the decoding of two or more of the codewords fails, the memory controller generates second XOR data, and corrects the value of one of the bits corresponding to a codeword whose decoding failed, based on the second XOR data.

The patent application was filed on March 2, 2020 (16/806,322).

Pattern forming and method of manufacturing semiconductor
Kioxia Corporation, Minato-ku, Japan, has been assigned a patent (11,024,510) developed by Imamura, Tsubasa, Kuwana Mie, Japan, for pattern forming method and method of manufacturing semiconductor device.

The abstract of the patent published by the U.S. Patent and Trademark Office states: According to one embodiment, a pattern forming method includes forming an organic layer on a first layer. The organic layer has a first region having a first thickness and a first width, a second region having a second thickness and a second width, and a third region located between the first region and the second region. The third region has a third thickness less than each of the first thickness and the second thickness and a third width. A second layer containing silicon oxide is then formed on a surface of the organic layer in a process chamber of a reactive ion etching device. The third region is then etched in the process chamber using the second layer as a mask.

The patent application was filed on February 26, 2020 (16/801,879).

Semiconductor memory
Kioxia Corporation, Minato-ku, Japan, has been assigned a patent (11,024,374) developed by Kawasumi, Atsushi, Fujisawa Kanagawa, Japan, for a semiconductor memory device.

The abstract of the patent published by the U.S. Patent and Trademark Office states: A semiconductor memory device of an embodiment includes: a first wiring disposed at a first level and extending in a first direction, a second and third wirings disposed at a second level and extending in the first direction, a plurality of fourth wirings disposed at a third level and extending in a third direction, a plurality of first resistive change elements disposed in intersection regions of the first and fourth wirings, a plurality of second resistive change elements disposed in intersection regions between the second wiring and the third wiring and the fourth wirings, a first driving circuit electrically connected to the first wiring, a second driving circuit electrically connected to the second wiring, and a third driving circuit electrically connected to the third wiring, and a control circuit that controls the first driving circuit, the second driving circuit, and the third driving circuit, and also the fourth wirings.

The patent application was filed on September 4, 2019 (16/560,554).

Nonvolatile semiconductor memory
Kioxia Corporation, Minato-ku, Japan, has been assigned a patent (11,024,360) developed by Watanabe, Toshifumi, Yokohama Kanagawa, Japan, and Abiko, Naofumi, Kawasaki Kanagawa, Japan, for a nonvolatile semiconductor memory device.

The abstract of the patent published by the U.S. Patent and Trademark Office states: A semiconductor memory device includes a memory cell, a word line connected to the memory cell, a source line connected to the memory cell, a bit line connected to the memory cell, and a control circuit configured to perform a read operation on the memory cell. During the read operation, the control circuit applies to the word line a first voltage, a second voltage greater than the first voltage after applying the first voltage, and a third voltage greater than the first voltage and smaller than the second voltage after applying the second voltage, and applies to the source line a fourth voltage according to a timing at which the second voltage is applied to the word line, a fifth voltage smaller than the fourth voltage after applying the fourth voltage, and a sixth voltage greater than the fifth voltage after applying the fifth voltage.

The patent application was filed on February 24, 2020 (16/799,402).

Memory system
Kioxia Corporation, Minato-ku, Japan, has been assigned a patent (11,017,837) developed by Hashimoto, Toshifumi, Fujisawa Kanagawa, Japan, for a memory system.

The abstract of the patent published by the U.S. Patent and Trademark Office states: According to one embodiment, a memory system includes: a semiconductor memory including a memory cell array, the memory cell array including a memory cell, and a controller configured to issue a first read command sequence after a lapse of a first time period from access to the semiconductor memory, and issue a second read command sequence after a lapse of a second time period from access to the semiconductor memory. When the controller issues the first read command sequence, the semiconductor memory applies a first voltage and a second voltage to the memory cell. When the controller issues the second read command sequence, the semiconductor memory applies a third voltage and a fourth voltage to the memory cell.

The patent application was filed on March 9, 2020 (16/812,944).

Memory system
Kioxia Corporation, Minato-ku, Japan, has been assigned a patent (11,016,663) developed by Wang, Ge, Yokohama Kanagawa, Japan, for a memory system.

The abstract of the patent published by the U.S. Patent and Trademark Office states: A memory system includes a nonvolatile memory, a controller, and a temperature sensor. The controller includes an interface circuit that controls an access to the nonvolatile memory. The temperature sensor measures a temperature of the memory system. The controller is configured to acquire a first temperature from the temperature sensor, acquire a first parameter set corresponding to the first temperature from parameter information including a plurality of parameter sets respectively corresponding to plurality of temperatures, and set the first parameter set in the interface circuit.

The patent application was filed on March 3, 2020 (16/807,845).

Semiconductor memory and method for manufacturing
Kioxia Corporation, Minato-ku, Japan, has been assigned a patent (11,014,256) developed by Sasaki, Toshiyuki, Yokkaichi Mie, Japan, for semiconductor memory device and method for manufacturing same.

The abstract of the patent published by the U.S. Patent and Trademark Office states: According to one embodiment, the stacked body includes a plurality of stacked units and a first intermediate layer. Each of the stacked units includes a plurality of electrode layers and a plurality of insulating layers. Each of the insulating layers is provided between the electrode layers. The first intermediate layer is provided between the stacked units. The first intermediate layer is made of a material different from the electrode layers and the insulating layers. The plurality of columnar portions includes a channel body extending in a stacking direction of the stacked body to pierce the stacked body, and a charge storage film provided between the channel body and the electrode layers.

The patent application was filed on May 12, 2020 (16/872,485).

Semiconductor storage
Kioxia Corporation, Minato-ku, Japan, has been assigned a patent (11,011,699) developed by Komura, Masanori, Kuwana Mie, Japan, and Tsukamoto, Takayuki, Yokkaichi Mie, Japan, for a semiconductor storage device.

The abstract of the patent published by the U.S. Patent and Trademark Office states: A semiconductor storage device includes first to third wirings extending in a first direction and adjacent in a second direction intersecting the first direction, fourth to sixth wirings extending in the second direction and adjacent in the first direction, memory cells each having one end connected to one of the first to third wirings and the other end connected to one of the fourth to sixth wirings, a circuit configured to output a first voltage, second and third voltages higher than the first voltage, a fourth voltage higher than the second voltage and the third voltage, and a fifth voltage higher than the fourth voltage. In a write operation for memory cells connected to the first and fourth wirings, the first, fourth, second, fifth and third voltages are transferred to the first, second, third, fourth, and fifth wirings, respectively, and the third voltage is transferred to the sixth wiring.

The patent application was filed on March 3, 2020 (16/807,770).

Semiconductor device having first and second terminals
Kioxia Corporation, Minato-ku, Japan, has been assigned a patent (11,011,484) developed by Wakioka, Hiroyuki, Yokkaichi Mie, Japan, for semiconductor device having first and second terminals.

The abstract of the patent published by the U.S. Patent and Trademark Office states: A semiconductor device includes a first substrate and a second substrate that is stacked on a first surface of the first substrate in a stacking direction and includes a second surface facing the first surface. A plurality of first terminals is provided on the first surface of the first substrate. A plurality of second terminals is provided on the second surface of the second substrate. A plurality of metallic portions is respectively provided between the plurality of first terminals and the plurality of second terminals. In a cross-section substantially perpendicular to the stacking direction, at least one of (i) each of the plurality of first terminals or (ii) each of the plurality of second terminals (a) includes a recessed portion in a first direction toward an adjacent first terminal or second terminal or (b) includes a projecting portion in a second direction intersecting with the first direction.

The patent application was filed on February 24, 2020 (16/799,024).

Semiconductor memory
Kioxia Corporation, Minato-ku, Japan, has been assigned a patent (11,011,239) developed by Shibata, Noboru, Kawasaki Kanagawa, Japan, Uchikawa, Hironori, and Shibuya, Taira, Fujisawa Kanagawa, Japan, for a semiconductor memory.

The abstract of the patent published by the U.S. Patent and Trademark Office states: A semiconductor memory according to an embodiment includes first and second memory cells, first and second memory cell arrays, first and second word lines, and controller. The first and second memory cell array include the first and second memory cells, respectively. The first and second word lines are coupled to the first and second memory cells, respectively. Data of six or more bits including a first bit, a second bit, a third bit, a fourth bit, a fifth bit, and a sixth bit is stored with the use of a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.

The patent application was filed on December 20, 2019 (16/724,100).

Semiconductor memory device with erase control
Kioxia Corporation, Minato-ku, Japan, has been assigned a patent (11,011,237) developed by Tsuda, Muneyuki, Ichinomiya, Japan, for a semiconductor memory device with erase control.

The abstract of the patent published by the U.S. Patent and Trademark Office states: A semiconductor memory device includes: a memory cell array including a plurality of conductive layers, a semiconductor layer, and charge accumulating sections, and a control circuit that executes an erase operation. The erase operation includes an erase mode that executes a first erase flow. The first erase flow includes: a first write operation in which a first program voltage is applied to the plurality of conductive layers, a first erase operation that is executed after the first write operation, and in which, while a first voltage is applied to a first conductive layer, a voltage higher than the first voltage is applied to the second conductive layer, and a second erase operation that is executed after the first erase operation, and in which, while the first voltage is applied to a second conductive layer, a voltage higher than the first voltage is applied to the first conductive layer.

The patent application was filed on February 11, 2020 (16/787,368).

Semiconductor storage device
Kioxia Corporation, Minato-ku, Japan, has been assigned a patent (11,011,211) developed by Komai, Hiromitsu, Kamakura Kanagawa, Japan, for a semiconductor storage device.

The abstract of the patent published by the U.S. Patent and Trademark Office states: A semiconductor storage device includes a plurality of memory cells and a plurality of bit lines connected thereto, a plurality of sense amplifier units respectively connected to the plurality of bit lines, and a cache memory connected to the plurality of sense amplifier units. Each sense amplifier unit includes a sense node and a latch in which data transferred onto the sense node from a corresponding bit line is latched. First data latched in a first sense amplifier unit among the plurality of sense amplifier units is transferred to the cache memory, and second data latched in a second sense amplifier unit among the plurality of sense amplifier units is transferred to the sense node of the first second sense amplifier unit. Thereafter, the second data is latched in the first sense amplifier unit and transferred to the cache memory.

The patent application was filed on February 28, 2020 (16/804,956).

Dicing method and laser processing
Kioxia Corporation, Minato-ku, Japan, has been assigned a patent (11,004,743) developed by Fujita, Tsutomu, Yokkaichi Mie, Japan, and Ono, Takanobu, Kuwana Mie, Japan, for dicing method and laser processing apparatus.

The abstract of the patent published by the U.S. Patent and Trademark Office states: According to one embodiment, a dicing method is provided. The dicing method includes detecting a first distance between a first portion of a substrate and a first substrate information detection unit. The method also includes detecting a second distance between a second portion of the substrate a second substrate information detection unit, the second portion different from the first portion. Distance information is calculated between the substrate and a processing lens, which is located farther from the second substrate information detection unit than from the first substrate information detection unit, based on the detected first distance and the detected second distance, and the substrate is irradiated with laser light from the processing lens based on the distance information.

The patent application was filed on October 24, 2018 (16/169,466).

Semiconductor device
Kioxia Corporation, Minato-ku, Japan, has been assigned a patent (11,004,731) developed by Miyano, Yumiko, Shinagawa Tokyo, Japan, for a semiconductor device.

The abstract of the patent published by the U.S. Patent and Trademark Office states: According to one embodiment, a semiconductor device includes a base, a memory cell region on the base comprising a first plurality of conductive layers and a second plurality of insulating layers, wherein an insulating layer extends between, and separates, each two adjacent conductive layers of the first plurality of conductive layers. A first stacked body and a second stacked body are located on the base, and includes a plurality of insulating layers and a plurality of conductive layers fewer than the number of first conductive layers, and an insulating layer extends between, and separates, each two adjacent conductive layers of the plurality of conductive layers in each stacked body. The end portions of the stacked bodies include a stair portion having a stair-like shape wherein a surface of each of the conductive layers thereof is exposed.

The patent application was filed on September 19, 2018 (16/135,686).

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