Cypress Semiconductor Assigned Six Patents

Silicon-oxide-nitride-oxide-silicon based multi level non-volatile memory
Cypress Semiconductor Corporation, San Jose, CA, has been assigned a patent (11,017,851) developed by Prabhakar, Venkataraman, Pleasanton, CA, Ramkumar, Krishnaswamy, Agrawal, Vineet, Hinh, Long, Saha, Swatilekha, San Jose, CA, Samanta, Santanu Kumar, West Bengal, India, Amundson, Michael, Woodinville, WA, and Kapre, Ravindra, San Jose, CA, for “silicon-oxide-nitride-oxide-silicon based multi level non-volatile memory device and methods of operation thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A semiconductor device that has a semiconductor-oxide-nitride-oxide-semiconductor (SONOS) based non-volatile memory (NVM) array including NVM cells arranged in rows and columns, in which NVM transistors of the NVM cells are configured to store N.times.analog values corresponding to the N.times.levels of their drain current (I.sub.D) or threshold voltage (V.sub.T) levels, digital-to-analog (DAC) function that receives and converts digital signals from external devices, column multiplexor (mux) function that is configured to select and combine the analog value read from the NVM cells, and analog-to-digital (ADC) function that is configured to convert analog results of the column mux function to digital values and output the digital values.”

The patent application was filed on March 24, 2020 (Appl. No.16/827,948).

USB type-C sideband signal interface circuit
Cypress Semiconductor Corporation, San Jose, CA, has been assigned a patent (10,990,560) developed by Khamesra, Arun, Bangalore, India, Nayak, Anup, Fremont, CA, Mondal, Partha, Paschim Medinipur, India, Vispute, Hemant Prakash, Bangalore, India, and Konduru, Ravi, Bengaluru, India, for an “USB type-C sideband signal interface circuit.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A USB-C controller, disposed on an integrated circuit (IC) comprises a first pair of terminals to communicate with a first communication protocol that is other than USB, a second pair of terminals to communicate with a second communication protocol that is other than USB, and a third pair of terminals, each of which is to be coupled to a corresponding SBU1 terminal or SBU2 terminal of a Type-C receptacle. The USB-C controller further includes: a multiplexer to selectively couple the first pair of terminals to the third pair of terminals and the second pair of terminals to the third pair of terminals: and logic to control the multiplexer according to a mode enabled within a configuration channel (CC) signal.”

The patent application was filed on May 17, 2019 (Appl. No.16/415,116).

Ferroelectric random access memory sensing scheme
Cypress Semiconductor Corporation, San Jose, CA, has been assigned a patent (10,978,127) developed by DeVilbiss, Alan D., and Lachman, Jonathan, Colorado Springs, CO, for a “ferroelectric random access memory sensing scheme.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Semiconductor memory devices and methods of operating the same are provided. The method of operation may include the steps of selecting a ferroelectric memory cell for a read operation, coupling a first pulse signal to interrogate the selected ferroelectric memory cell, the selected ferroelectric memory cell outputting a memory signal to a bit-line in response to the first pulse signal, coupling the memory signal to a first input of a sense amplifier via the bit-line, electrically isolating the sense amplifier from the selected ferroelectric memory cell, and enabling the sense amplifier for sensing after the sense amplifier is electrically isolated from the selected ferroelectric memory cell. Other embodiments are also disclosed.”

The patent application was filed on February 7, 2020 (Appl. No.16/784,712).

Reducing charge loss in non-volatile memories
Cypress Semiconductor Corporation, San Jose, CA, has been assigned a patent (10,957,703) developed by Singh, Pawan Kishore, Santa Clara, CA, Shetty, Shivananda, San Jose, CA, and Pak, James, Sunnyvale, CA, for a “method of reducing charge loss in non-volatile memories.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”An example embodiment comprises a method for fabrication of a non-volatile memory (NVM) device. An isolation structure is formed in a substrate between first and second locations for first and second NVM cells. A common charge trapping layer is formed as a continuous structure over the substrate, where a first portion of the charge trapping layer is disposed directly over the isolation structure and second portions of the charge trapping layer are disposed directly over the first and second substrate locations. Nitrogen doping of the first portion of the charge trapping layer is performed, where after the nitrogen doping is performed the first portion of the charge trapping layer includes a higher nitrogen concentration than the second portions. The first and second NVM cells are then formed over the first and second substrate locations, where the first and second NVM cells include the second portions of the charge trapping layer.”

The patent application was filed on August 6, 2018 (Appl. No.16/056,183).

Voltage protection for universal serial bus Type-C (USB-C) connector
Cypress Semiconductor Corporation, San Jose, CA, has been assigned a patent (10,950,987) developed by Bodnaruk, Nicholas Alexander, Sunnyvale, CA, and Mattos, Derwin W., San Mateo, CA, for “voltage protection for universal serial bus Type-C (USB-C) connector systems.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”An electronic device includes a first switch configured to connect a first sideband use (SBU) terminal of a Universal Serial Bus Type-C (USB-C) controller to a first SBU terminal of a USB-C receptacle. The electronic device also includes a second switch configured to connect a second sideband use (SBU) terminal of the USB-C controller to a second SBU terminal of the USB-C receptacle. The electronic device further includes a voltage protection circuit configured to deactivate one or more of the first switch and the second switch when a voltage exceeding a predetermined threshold is detected. The voltage protection circuit includes a first set of diodes coupled to the first SBU terminal of the USB-C controller and a second set of diodes coupled to the second SBU terminal of the USB-C controller.”

The patent application was filed on June 20, 2019 (Appl. No.16/446,870).

Block mapping for storage device
Cypress Semiconductor Corporation, San Jose, CA, has been assigned a patent (10,949,340) developed by Okada, Shinsuke, Kawashaki, Japan, Atri, Sunil, Cupertino, CA, and Saito, Hiroyuki, Kawasaki, Japan, for “block mapping systems and methods for storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”An overlaid erase block (EB) mapping scheme for a flash memory provides efficient wear-leveling and reduces mount operation latency. The overlaid EB mapping scheme maps a first type of EB onto one of a plurality of physical erase blocks, in a corresponding portion of the flash memory. The first type of EB includes a plurality of pointers. The overlaid EB mapping scheme also maps each of second and third types of EBs onto one of the physical EBs that is not mapped to the first type of EB. The second type of EBs store system management information and the third type of EBs store user data. When the flash memory is started up, the overlaid EB mapping scheme scans the corresponding portion to locate the first type of EB, locates the system EBs using the pointers, and locates the data EBs using the system management information.”

The patent application was filed on May 18, 2018 (Appl. No.15/984,071).