R&D: All-Bit-Line Read Scheme With Locking Bit-Line and Amplifying Sense Node in NAND Flash

IEEE Access has published an article written by Jun Ho An, School of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea, and Memory Division, Samsung Electronics Company Ltd., Hwaseong, South Korea, Jin Young Chun, Memory Division, Samsung Electronics Company Ltd., Hwaseong, South Korea, Hyun Kook Park, School of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea, and Memory Division, Samsung Electronics Company Ltd., Hwaseong, South Korea, and Seong-Ook Jung, School of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea.

Abstract: “A NAND flash memory senses a cell current in the range of tens of nA, which is smaller than other nonvolatile memories in the read operation. Because of the small cell current, it is difficult to improve the latency and accuracy of the read operation. The improvement of read latency has been a major challenge for the all-bit-line (ABL) sensing architecture because the BL coupling capacitance caused by the off cell limits the BL pre-charge time. In this paper, a high-speed BL pre-charge scheme with an off-cell-like BL locking (OCBLL) is proposed to reduce the BL coupling capacitance between the off-cell BL and the adjacent BL. The deviation of the latch trip voltage caused by the variations in process, voltage, and temperature (PVT) presents another challenge because the deviation increases the read error owing to the small cell current. A sense-out-node amplification (SOA) scheme is proposed to amplify the voltage of the sense-out-node according to the cell current. The SOA scheme generates a large voltage difference despite the small cell current difference. In the simulation with HSPICE models under the same BL-to-BL coupling ratio, it is found that the proposed schemes improve the speed of the BL pre-charge operation by 75% and reduce the read error by 57%.“