Macronix International Assigned Five Patents

Three dimensional memory
Macronix International Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (10,930,669) developed by Hu, Chih-Wei, Toufen, Taiwan, Yeh, Teng-Hao, and Jiang, Yu-Wei, Hsinchu, Taiwan, for “three dimensional memory device and method for fabricating the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A three-dimensional memory device includes a substrate, conductive layers and insulating layers, a storage layer, a first channel, a second channel and a first conductive plug. The conductive layers and insulating layers are alternately stacked over the substrate to form a multi-layer stacked structure. The storage layer penetrates through the multi-layer stacked structure, and has a first string portion and a second string portion that are spaced from each other. The first channel is located on a lateral side of the first string portion. The second channel is located on a lateral side of the second string portion. The first channel and the second channel have an upper channel portion and a lower channel portion. The first conductive plug is interconnected between the upper channel portion and the lower channel portion.”

The patent application was filed on February 12, 2019 (16/273,301).

Crenellated charge storage structures for 3D NAND
Macronix International Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (10,916,560) developed by Lai, Erh-Kun, Longling Shiang, Taiwan, and Lung, Hsiang-Lan, Kaohsiung, Taiwan, for a “crenellated charge storage structures for 3D NAND.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory device comprises a stack of conductive strips separated by insulating layers on a substrate, and a vertical channel structure disposed in a hole through the stack of conductive strips to the substrate. A vertical channel structure is disposed in a hole through the stack of conductive strips to the substrate. Charge storage structures are disposed at cross points of the conductive strips and the vertical channel structure, the charge storage structures including multiple layers of materials. The insulating layers have sidewalls recessed from the vertical channel structure. A charge storage layer of the multiple layers of materials of the charge storage structures lines sidewalls of the insulating layers. Dielectric material is disposed between the vertical channel structure and the charge storage layer on sidewalls of the insulating layers.”

The patent application was filed on January 14, 2019 (16/247,079).

Memory storage and operation method
Macronix International Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (10,891,222) developed by Wei, Ming-Liang, Kaohsiung, Taiwan, for “memory storage device and operation method thereof for implementing inner product operation.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory storage device includes: a memory array for generating a cell current dependent to an input and transconductance of memory cells of the memory array, a reference array for generating a reference current, an ADC for performing analog-digital-conversion on the cell current based on the reference current to generate a digital output, and a memory controller for generating an output based on the input and the digital output of the ADC. The output of the memory controller indicates an inner product of the input and a weight, the weight including a positive weight and a negative weight. The positive weight is implemented by the transconductance of the memory cells of the memory array. The negative weight is implemented by transconductance of reference cells of the reference array or implemented by a shifting number of a shifter in the memory controller.”

The patent application was filed on December 24, 2018 (16/231,681).

Pitch scalable 3D NAND
Macronix International Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (10,840,254) developed by Lung, Hsiang-Lan, Ardsley, NY, for a “pitch scalable 3D NAND.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory includes a plurality of levels of word lines interleaved with a plurality of levels of channel lines. Horizontal data storage levels are disposed between the plurality of levels of word lines and the plurality of levels of channel lines, the data storage levels including respective arrays of data storage regions in cross points of word lines and channel lines in adjacent levels of the plurality of levels of word lines and the plurality of levels of channel lines. Respective arrays of holes outside of the cross points are disposed in the channel line and word line levels. The channel lines and word lines have sides defined by undercut etch perimeters, along with air gaps or voids between the channel lines and word lines in each level. The word lines, bit lines and data storage nodes in each layer are vertically self-aligned.”

The patent application was filed on November 29, 2018 (16/204,284).

Semiconductor structure and manufacturing
Macronix International Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (10,811,427) developed by Jiang, Yu-Wei, Hsinchu, Taiwan, Chang, Kuo-Pin, and Chen, Chieh-Fang, Zhubei, Taiwan, for “semiconductor structure and manufacturing method thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A semiconductor structure includes a substrate, conductive layers, dielectric layers, an isolation structure, a first memory structure, and a second memory structure. The conductive layers and the dielectric layers are interlaced and stacked on the substrate. The isolation structure is disposed on the substrate and through the conductive layers and the dielectric layers. Each of the first and second memory structures has a radius of curvature. The first and second memory structures penetrate through the conductive layers and the dielectric layers and are disposed on opposite sidewalls of the isolation structure. Each of the first and second memory structures includes protecting structures and a memory structure layer including a memory storage layer. The protecting structures are disposed at two ends of the memory storage layer, and an etching selectivity to the protecting structures is different from an etching selectivity to the memory storage layer.”

The patent application was filed on April 18, 2019 (16/387,650).