IBM Assigned Fourteen Patents

Writing multiple levels in phase change memory
IBM Corp., Armonk, NY, has been assigned a patent (10,943,658) developed by Lam, Chung H., Peekskill, NY, Lewis, Scott C., Essex Junction, VT, Maffitt, Thomas M., Burlington, VT, and Morrish, Jack, Shelburne, VT, for “writing multiple levels in a phase change memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Structures and methods for a multi-bit phase change memory, are provided herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.”

The patent application was filed on November 11, 2019 (16/679,782).

Bi-layer composite phase-change-memory cell
IBM Corp., Armonk, NY, has been assigned a patent (10,937,961) developed by Ok, Injo, Loudonville, NY, Na, Myung-Hee, Lagrangeville, NY, Saulnier, Nicole, Slingerlands, NY, and Pranatharthiharan, Balasubramanian, Watervliet, NY, for “structure and method to form bi-layer composite phase-change-memory cell.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A Phase-change-memory (PCM) cell and method of forming the PCM are provided. In an illustrative embodiment, a method of forming a PCM cell includes forming a first layer of a first germanium-antimony-tellurium (GST) type material over at least a portion of the bottom and sides of a pore through a dielectric layer of low dielectric material to a bottom electrode. The method also includes forming a second layer of a second GST type material over the first GST type material along the bottom and sides of the pore over the bottom electrode. The first GST type material is different from the second GST type material.”

The patent application was filed on November 6, 2018 (16/182,293).

Writing multiple levels in phase change memory
IBM Corp., Armonk, NY, has been assigned a patent (10,937,496) developed by Lam, Chung H., Peekskill, NY, Lewis, Scott C., Essex Junction, VT, Maffitt, Thomas M., Burlington, VT, and Morrish, Jack, Shelburne, VT, for “writing multiple levels in a phase change memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.”

The patent application was filed on July 30, 2019 (16/526,273).

Crystallized silicon vertical diode on BEOL for access device for confined PCM arrays
IBM Corp., Armonk, NY, has been assigned a patent (10,930,705) developed by Carta, Fabio, Pleasantville, NY, Lam, Chung H., Peekskill, NY, BrightSky, Matthew J., Pound Ridge, NY, and Hekmatshoartabari, Bahman, White Plains, NY, for a “crystallized silicon vertical diode on BEOL for access device for confined PCM arrays.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A method is presented for integrating an electronic component in back end of the line (BEOL) processing. The method includes forming a first electrode over a semiconductor substrate, forming a first electrically conductive material over a portion of the first electrode, forming a second electrically conductive material over the first electrically conductive material, where the first and second electrically conductive materials define a p-n junction, depositing a phase change material over the p-n junction, and forming a second electrode over the phase change material.”

The patent application was filed on March 28, 2018 (15/938,625).

Advanced interconnects containing IMT liner
IBM Corp., Armonk, NY, has been assigned a patent (10,930,589) developed by Maniscalco, Joseph F., Lake Katrine, NY, Kim, Andrew Tae, Poughkeepsie, NY, Li, Baozhen, South Burlington, VT, and Yang, Chih-Chao, Glenmont, NY, for an “advanced interconnects containing an IMT liner.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”An interconnect structure is provided that includes a liner located between an electrically conductive structure and an interconnect dielectric material layer. The liner is composed of a phase change material that is insulating at a first temperature, and becomes conductive at a second temperature that is higher than the first temperature. The liner that is composed of such a phase change material is referred to as an (insulator-to/from metal transition (IMT) liner. In the present application, an entirety of, or a portion of, the IMT liner may be changed from an insulating phase to a conductive phase by increasing the temperature (i.e., heating) of the liner so as to provide a redundancy path in which electrons can flow.”

The patent application was filed on September 27, 2019 (16/585,672).

Vertically oriented memory structure
IBM Corp., Armonk, NY, has been assigned a patent (10,903,422) developed by Leobandung, Effendi, Stormville, NY, for a “vertically oriented memory structure.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A method for fabricating a semiconductor device including a vertically oriented memory structure includes forming at least one pillar including phase-change memory (PCM) material on at least one electrode, forming a plurality of spacers on the electrode and along sidewalls of the pillar, and forming, by processing the plurality of spacers and the pillar, a modified pillar having a vertically oriented dumbbell shape associated with a vertically oriented PCM memory structure.”

The patent application was filed on April 11, 2019 (16/381,406).

Low resistance electrode for high aspect ratio confined PCM cell in BEOL
IBM Corp., Armonk, NY, has been assigned a patent (10,903,418) developed by Bao, Ruqiang, Niskayuna, NY, and Saulnier, Nicole, Slingerlands, NY, for a “low resistance electrode for high aspect ratio confined PCM cell in BEOL.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A phase change material (PCM) device is described. A non-limiting example of the PCM device includes a bottom electrode including a low resistivity material and a PCM material over the bottom electrode. The PCM device has a top electrode over the PCM material.”

The patent application was filed on November 19, 2018 (16/194,662).

Phase change memory with gradual conductance change
IBM Corp., Armonk, NY, has been assigned a patent (10,903,273) developed by Cheng, Kangguo, Schenectady, NY, for a “phase change memory with gradual conductance change.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A phase change memory cell is provided that includes a phase change material-containing structure sandwiched between first and second electrodes. The phase change material-containing structure has an electrical conductance that changes gradually and thus may be used in analog or neuromorphic computing. The phase change material-containing structure includes two phase change material pillars that are composed of different phase change materials that exhibit an opposite change of electrical resistance (or inversely electrical conductance) during a SET operation and a RESET operation.”

The patent application was filed on January 4, 2019 (16/240,233).

Granular variable impedance tuning
IBM Corp., Armonk, NY, has been assigned a patent (10,897,239) developed by Saetow, Anuwat, Austin, TX, Cadigan, David D., Danbury, CT, Huott, William V., Holmes, NY, and McPadden, Adam J., Underhill, VT, for a “granular variable impedance tuning.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A method comprises activating an interval timer to expire in a calibration time interval and, in response to the timer expiring, performing an impedance analysis of an electronic network. The impedance analysis can use time-domain reflectometry. Based on the analysis, the method can calibrate a variable impedance device to have a first impedance and re-activate the timer. The method can perform a second impedance analysis based on calibrating the variable impedance device. The method can include determining a drift rate and modifying the calibration time interval. The variable impedance device can comprise a phase-change material (PCM) and the time interval can correspond to a retention time of the PCM and/or a dynamic drift rate. A system comprising a segment of an electronic network, a timer, a variable impedance device, and an impedance tuning system can embody operations of the method.”

The patent application was filed on September 6, 2019 (16/563,104).

Integration of confined phase change memory with threshold switching material
IBM Corp., Armonk, NY, has been assigned a patent (10,892,413) developed by Bruce, Robert L., Carta, Fabio, White Plains, NY, Kim, Wanki, Westchester, NY, and Lam, Chung H., Peekskill, NY, for an “integration of confined phase change memory with threshold switching material.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A phase change memory array and method for fabricating the same. The phase change memory array includes a plurality of bottom electrodes, top electrodes, and memory pillars. Each of the memory pillars includes phase change material surrounded by a dielectric casing. The phase change material is positioned between, and in series circuit with, a respective bottom electrode from the bottom electrodes and a respective top electrode from the top electrodes. A continuous layer of selector material is positioned between the memory pillars and the plurality of bottom electrodes. The selector material is configured to conduct electricity only when a voltage across the selector material exceeds a voltage threshold.”

The patent application was filed on January 17, 2017 (15/408,392).

Selective phase change material
IBM Corp., Armonk, NY, has been assigned a patent (10,886,464) developed by BrightSky, Matthew J., Pound Ridge, NY, Bruce, Robert, White Plains, NY, and Masuda, Takeshi, Yorktown Heights, NY, for a “selective phase change material growth in high aspect ratio dielectric pores for semiconductor device fabrication.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A metal liner is deposited conformally to a pore within a first dielectric material of a semiconductor device. The pore extends through the first dielectric material to a top surface of a first metal electrode. The metal liner is etched such that the metal liner only substantially remains on sidewalls of the pore. A phase change material is selectively deposited within the pore of the first dielectric layer to substantially fill the pore with the phase change material. The selective deposition of the phase change material produces a growth rate of phase change material on the metal liner at a substantially greater rate than a growth rate of the phase change material on exposed surfaces of the first dielectric material.”

The patent application was filed on October 3, 2018 (16/151,052).

Fabrication of phase change memory cell in integrated circuit
IBM Corp., Armonk, NY, has been assigned a patent (10,840,447) developed by Li, Baozhen, South Burlington, VT, Yang, Chih-Chao, Glenmont, NY, Kim, Andrew Tae, Poughkeepsie, NY, and Linder, Barry, Hastings-on-Hudson, NY, for a “fabrication of phase change memory cell in integrated circuit.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A phase change memory (PCM) cell in an integrated circuit and a method of fabricating it involve depositing a layer of PCM material on a surface of a dielectric, and patterning the layer of PCM material into a plurality of PCM blocks. Heater material is formed on both sidewalls of each of the plurality of the PCM blocks to form a plurality of PCM cells. Each of the plurality of the PCM blocks and the heater material on both the sidewalls represents a PCM cell. An additional layer of the dielectric is deposited above and between the plurality of the PCM cells, and trenches are formed in the dielectric. Trenches are formed in contact with each side of each of the plurality of the PCM cells. Metal is deposited in each of the trenches. Current flow in the metal heats the heater material of one of the PCM cells.”

The patent application was filed on March 12, 2019 (16/299,313).

3D phase change memory
IBM Corp., Armonk, NY, has been assigned a patent (10,833,269) developed by Wang, Wei, Yorktown Heights, NY, Pranatharthiharan, Balasubramanian, Watervliet, NY, Ok, Injo, Loudonville, NY, and Brew, Kevin W., Albany, NY, for a “3D phase change memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A method is presented for constructing a three-dimensional (3D) stack phase change memory (PCM) device. The method includes forming a plurality of stack layers over a plurality of conductive lines, the plurality of conductive lines formed within trenches of an inter-layer dielectric (ILD) forming isolation trenches extending through the plurality of stack layers, etching the plurality of stack layers to define an opening, filling the opening with at least a phase change material, and constructing vias to the plurality of conductive lines.”

The patent application was filed on May 7, 2019 (16/405,133).

Phase change memory array with integrated polycrystalline diodes
IBM Corp., Armonk, NY, has been assigned a patent (10,833,123) developed by Hekmatshoartabari, Bahman, White Plains, NY, Lam, Chung H., Peekskill, NY, Carta, Fabio, Yorktown Heights, NY, and BrightSky, Matthew J., Pound Ridge, NY, for a “phase change memory array with integrated polycrystalline diodes.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A method for deactivating memory cells affected by the presence of grain boundaries in polycrystalline selection devices includes crystallizing a semiconductor layer in a diode stack to form a polycrystalline layer for selection diodes formed in a crossbar array. To achieve a crystalline state in phase change memory elements coupled to corresponding selection diodes perform an anneal. Memory cells having shunted selection diodes due to grain boundaries are identified by scanning the array using sense voltages. A second voltage larger than the sense voltages is applied to the phase change memory elements gated by the shunted selection diodes such that the phase change memory elements gated by the shunted diodes achieve a permanently high resistive state.”

The patent application was filed on January 15, 2019 (16/248,010).