Radian Memory Systems Assigned Seven Patents

Zones in nonvolatile or persistent memory with configured write parameters
Radian Memory Systems, Inc., Calabasas, CA, has been assigned a patent (11,003,586) developed by Lercari, Robert, Thousand Oaks, CA, Chen, Alan, Simi Valley, CA, Jadon, Mike, Manhattan Beach, CA, Robertson, Craig, Simi Valley, CA, and Kuzmin, Andrey V., Moscow, Russia, for “zones in nonvolatile or persistent memory with configured write parameters.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.”

The patent application was filed on February 5, 2020 (Appl. No 16/783,106).

Nonvolatile memory with configurable zone/namespace parameters
and host-directed copying of data across zones/namespaces
Radian Memory Systems, Inc., Calabasas, CA, has been assigned a patent (10,996,863) developed by Kuzmin, Andrey V., Moscow, Russia, Chen, Alan, Simi Valley, CA, and Lercari, Robert, Thousand Oaks, CA, for “nonvolatile memory with configurable zone/namespace parameters and host-directed copying of data across zones/namespaces.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”This disclosure provides techniques for managing memory which match per-data metrics to those of other data or to memory destination. In one embodiment, wear data is tracked for at least one tier of nonvolatile memory (e.g., flash memory) and a measure of data persistence (e.g., age, write frequency (etc.) is generated or tracked for each data item. Memory wear management based on these individually-generated or tracked metrics is enhanced by storing or migrating data in a manner where persistent data is stored in relatively worn memory locations (e.g., relatively more-worn flash memory) while temporary data is stored in memory that is less worn or is less susceptible to wear. Other data placement or migration techniques are also disclosed.”

The patent application was filed on March 27, 2020 (Appl. No 16/832,834).

Nonvolatile memory controller
Radian Memory Systems, Inc., Calabasas, CA, has been assigned a patent (10,983,907) developed by Kuzmin, Andrey V., Moscow, Russia, Jadon, Mike, Manhattan Beach, CA, and Mathews, Richard M., Porter Ranch, CA, for a “nonvolatile memory controller that supports host selected data movement based upon metadata generated by the nonvolatile memory controller.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”This disclosure provides for host-controller cooperation in managing NAND flash memory. The controller maintains information for each erase unit which tracks memory usage. This information assists the host in making decisions about specific operations, for example, initiating garbage collection, space reclamation, wear leveling or other operations. For example, metadata can be provided to the host identifying whether each page of an erase unit has been released, and the host can specifically then command each of consolidation and erase using direct addressing. By redefining host-controller responsibilities in this manner, much of the overhead association with FTL functions can be substantially removed from the memory controller, with the host directly specifying physical addresses. This reduces performance unpredictability and overhead, thereby facilitating integration of solid state drives (SSDs) with other forms of storage. The disclosed techniques are especially useful for direct-attached and/or network-attached storage.”

The patent application was filed on March 28, 2020 (Appl. No 16/833,541).

Idealized nonvolatile or persistent memory based upon hierarchical address translation
Radian Memory Systems, Inc., Calabasas, CA, has been assigned a patent (10,977,188) developed by Lercari, Robert, Thousand Oaks, CA, Chen, Alan, Simi Valley, CA, Jadon, Mike, Manhattan Beach, CA, Robertson, Craig, Simi Valley, CA, and Kuzmin, Andrey V., Moscow, Russia, for “idealized nonvolatile or persistent memory based upon hierarchical address translation.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.”

The patent application was filed on February 3, 2020 (Appl. No 16/779,893).

Techniques for directed data migration
Radian Memory Systems, Inc., Calabasas, CA, has been assigned a patent (10,956,082) developed by Chen, Alan, Robertson, Craig, Simi Valley, CA, Lercari, Robert, Thousand Oaks, CA, and Kuzmin, Andrey V., Moscow, Russia, for “techniques for directed data migration.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A host stores ‘context’ metadata for logical block addresses (LBAs) in a manner tied to physical location. Notwithstanding log-structured or copy on write processes, the host is then provided with immediate context when the host is called upon to assist a memory controller with data identified by physical location, for example, for memory reconfiguration, garbage collection, wear leveling or other processes. The metadata for example can provide the host with insight as to which data may be moved to enhance performance optimization and where that data can be placed. In one embodiment, the host writes back one or more references that span multiple layers of indirection in concert with write of the underlying data, in another embodiment, the context can point to other metadata.”

The patent application was filed on December 4, 2019 (Appl. No 16/702,736).

Configuration of isolated regions or zones based upon underlying memory geometry
Radian Memory Systems, Inc., Calabasas, CA, has been assigned a patent (10,915,458) developed by Lercari, Robert, Thousand Oaks, CA, Chen, Alan, Simi Valley, CA, Jadon, Mike, Manhattan Beach, CA, Robertson, Craig, Simi Valley, CA, and Kuzmin, Andrey V., Moscow, Russia, for a “configuration of isolated regions or zones based upon underlying memory geometry.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.”

The patent application was filed on February 3, 2020 (Appl. No 16/779,918).

Flash memory controller
Radian Memory Systems, Inc., Calabasas, CA, has been assigned a patent (10,884,915) developed by Kuzmin, Andrey V., Moscow, Russia, Jadon, Mike, Manhattan Beach, CA, and Mathews, Richard M., Porter Ranch, CA, for a “flash memory controller to perform delegated move to host-specified destination.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”This disclosure provides for host-controller cooperation in managing NAND flash memory. The controller maintains information for each erase unit which tracks memory usage. This information assists the host in making decisions about specific operations, for example, initiating garbage collection, space reclamation, wear leveling or other operations. For example, metadata can be provided to the host identifying whether each page of an erase unit has been released, and the host can specifically then command each of consolidation and erase using direct addressing. By redefining host-controller responsibilities in this manner, much of the overhead association with FTL functions can be substantially removed from the memory controller, with the host directly specifying physical addresses. This reduces performance unpredictability and overhead, thereby facilitating integration of solid state drives (SSDs) with other forms of storage. The disclosed techniques are especially useful for direct-attached and/or network-attached storage.”

The patent application was filed on June 16, 2017 (Appl. No 15/625,956).