Seagate Assigned Eighteen Patents

Symbol pair encoding for data compression
Seagate Technology LLC, Fremont, CA, has been assigned a patent (10,911,064) developed by Xie, Hongmei, Milpitas, CA, and Haratsch, Erich Franz, San Jose, CA, for a “symbol pair encoding for data compression.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Methods, apparatuses, and computer-readable media for compressing data for storage or transmission. Input data is compressed in a first stage utilizing a first compression algorithm and the frequencies of occurrence of symbols and symbol pairs in the output from the first stage is calculated. The output from the first stage is then encoded to a final compressed bit string in a second stage utilizing a second compression algorithm based on the calculated frequencies of occurrence of the symbols and the symbol pairs.”

The patent application was filed on January 6, 2020 (16/734,904).

Storage compute appliance with user authentication and memory allocation capabilities
Seagate Technology LLC, Fremont, CA, has been assigned a patent (10,909,272) developed by Simonson, Dana Lynn, Owatonna, MN, Secatch, Stacey, Longmont, CO, Conklin, Kristofer C., Burnsville, MN, and Moss, Robert Wayne, Windsor, CO, for a “storage compute appliance with user authentication and memory allocation capabilities.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Method and apparatus for managing data in a data storage device configured as a storage compute appliance. In some embodiments, the data storage device has a controller circuit and a non-volatile memory (NVM) with an overall data storage capacity. A processor authenticates each of a plurality of authorized users of the NVM via data exchanges between a host device and the processor without reference to an external authentication authority device. Upon authentication, each authorized user is allocated a separate portion of the overall data storage capacity of the NVM using an allocation model. The size of at least one of the separate portions is subsequently adjusted based on an access history of the NVM. The storage device may be a key-value storage device so that a separate set of key values is provided to each authorized user to identify data blocks stored to and retrieved from the NVM.”

The patent application was filed on January 31, 2018 (15/885,144).

NAND flash reset control
Seagate Technology LLC, Fremont, CA, has been assigned a patent (10,909,051) developed by Canepa, Timothy, Los Gatos, CA, for a “NAND flash reset control.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Method and apparatus for managing a non-volatile memory (NVM). In some embodiments, a memory module has a memory module electronics (MME) circuit configured to program data to and read data from solid-state non-volatile memory cells of the NVM. A controller is adapted to communicate commands and data to the MME circuit via an intervening data bus. The controller operates to reset the MME circuit by issuing a reset command to the MME circuit over the data bus, activating a decoupling circuit coupled between the data bus and a reference line at a reference voltage level to remove capacitance from the data bus resulting from the reset command, and subsequently sensing a voltage on the data bus. In some cases, multiple MME circuits and NVMs may be arranged on a plurality of flash dies which are concurrently reset by the controller.”

The patent application was filed on June 1, 2017 (15/610,815).

Storage with actuated media player
Seagate Technology LLC, Fremont, CA, has been assigned a patent (10,902,879) developed by Mendonsa, Riyan Alex, Minneapolis, MN, Herdendorf, Brett R., Mound, MN, and Subramanian, Krishnan, Shakopee, MN, for a “storage system with actuated media player.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data storage library includes multiple storage cartridges arranged in a rack, read/write control electronics integrated within a media player assembly, and actuation means for achieving relative movement between the media player assembly and the multiple storage cartridges in the rack to allow the read/write control electronics within the media player assembly to selectively couple with and provide data access to at least a subset of the multiple storage cartridges.”

The patent application was filed on September 25, 2019 (16/581,981).

Thermal management of laser diode mode hopping for HAMR
Seagate Technology LLC, Fremont, CA, has been assigned a patent (10,902,876) developed by Tatah, Karim, Benakli, Mourad, Eden Prairie, MN, and Wessel, James Gary, Savage, MN, for a “thermal management of laser diode mode hopping for heat assisted media recording.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A method and apparatus provide for determining a temperature at a junction of a laser diode when the laser diode is operated in a lasing state that facilitates heat-assisted magnetic recording, comparing the junction temperature and an injection current supplied during the lasing state to stored combinations of junction temperature and injection current, and determining a likelihood of mode hopping occurring for the laser diode during the lasing state based on the comparison to stored combinations of junction temperature and injection current.”

The patent application was filed on December 16, 2019 (16/714,962).

Failure detection and data recovery in storage
Seagate Technology LLC, Fremont, CA, has been assigned a patent (10,901,866) developed by Aklik, Mehmet Emin, Goss, Ryan James, Khoueir, Antoine, and Lien, Nicholas Odin, Shakopee, MN, for “failure detection and data recovery in a storage system.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Systems and methods presented herein provide for failure detection and data recovery in a storage system. In one embodiment, a method operable in a storage system comprises locating failures in data blocks in storage area of a storage device, categorizing the failures into block groups, each block group comprising one or more data blocks having failures, and halting input/output (I/O) operations to data blocks in a first of the block groups due to the failures of the first block group. The method also includes detecting additional failures in one or more data blocks of other block groups remaining in the storage area, and determining when to fail the storage area of the storage device based on the detected failures.”

The patent application was filed on August 1, 2018 (16/052,108).

Self-healing in storage system where critical storage group is rebuilt with different raid geometry using remaining functioning drives
Seagate Technology LLC, Fremont, CA, has been assigned a patent (10,901,634) developed by Lingarajappa, Chetan Bendakaluru, Bangalore, India, for “self-healing in a storage system where critical storage group is rebuilt with different raid geometry using remaining functioning drives (in the critical storage group) that have not failed, and not all data, drained from the critical storage group, is stopped in the critical storage group that is rebuilt.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A storage system may include a plurality of logical storage units that each include a plurality of storage devices. One or more logical unit numbers may be stored across one or more of the plurality of logical storage units, and the logical unit numbers may be accessible by one or more host devices. A logical storage unit may include a plurality of storage devices. Upon detection of failure of a storage device of a logical storage unit, data of the logical storage unit is drained to one or more fault tolerant logical storage unit. The logical storage unit with the defective device is converted to a fault-tolerant logical storage unit using the available and non-defective devices. Data is rebalanced across the fault-tolerant logical storage units.”

The patent application was filed on January 12, 2018 (15/870,385).

Controller architecture for reducing on-die capacitance
Seagate Technology LLC, Fremont, CA, has been assigned a patent (10,896,721) developed by Chhabra, Nitin Kumar, Pune, India, for a “controller architecture for reducing on-die capacitance.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”The disclosed controller includes a DDR architecture that includes a dual-channel interface designed to include DQS IO ports configured to generate a first DQS signal that is a distance of substantially 0.125 times the period of a clock signal (.DELTA.T denoting the 0.125 of the period of the clock signal) ahead of a rising edge of the clock signal and a second DQS signal that is a distance of substantially 0.125 times the period of the clock signal behind the rising edge of a clock signal. If .DELTA.T is more than a tDQSS then .DELTA.T is set to tDQSS, where tDQSS is a maximum allowable time between either DQS signal and the rising edge of the clock signal.”

The patent application was filed on January 17, 2020 (16/746,365).

Negative thermal expansion layer for HAMR media
Seagate Technology LLC, Fremont, CA, has been assigned a patent (10,896,693) developed by Zhang, Lihong, Liu, Xiong, Singapore, Singapore, Wang, Hongbo, and Li, Xinwei, Fremont, CA, for a “negative thermal expansion layer for heat assisted magnetic recording media.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A stack comprises a substrate, a magnetic recording layer, and a negative thermal expansion layer disposed between the substrate and the magnetic recording layer. The negative thermal expansion layer is configured to reduce thermal profile changes of a surface of the stack opposite the substrate during a heat assisted magnetic recording write operation.”

The patent application was filed on March 9, 2017 (15/454,587).

Machine learning error prediction in storage arrays
Seagate Technology LLC, Fremont, CA, has been assigned a patent (10,896,114) developed by Savanur, Sunil, Maharashtra, India, for a “machine learning error prediction in storage arrays.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Systems and methods for machine learning error prediction in storage arrays are described. In one embodiment, the method includes monitoring events of at least a first storage drive array, analyzing the monitored events using machine learning, identifying failure events based at least in part on the analysis and operating a prediction model engine to predict potential errors in storage drive arrays, the prediction model engine being built based at least in part on the analysis of the monitored events or the identifying of the failure events, or both.”

The patent application was filed on May 23, 2018 (15/987,775).

Managing superparity storage location usage and coverage
Seagate Technology LLC, Fremont, CA, has been assigned a patent (10,896,091) developed by Zhang, Wei, Liu, Xiong, Ng, Choon Wei, and Ye, Zhi, Singapore, Singapore, for “managing superparity storage location usage and coverage.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A method includes storing a superset of data on a data storage medium along with a corresponding superset superparity. The superset of data includes multiple sets of data, and the corresponding superset superparity is calculated based on all of the multiple sets of data. The method also includes updating at least one subset of the superset of data. The subset has a subset superparity. The superset superparity is updated with the subset superparity, and the subset superparity and a location of the subset within the superset are employed to carry out error correction operations.”

The patent application was filed on May 30, 2019 (16/426,773).

Metadata recovery mechanism for page storage
Seagate Technology LLC, Fremont, CA, has been assigned a patent (10,896,088) developed by Velayuthaperumal, Gomathirajan Authoor, Bangalore Karnataka, India, Wolinski, Adam Thomas, Firestone, CO, Shellhamer, Jeffery L., Erie, CO, Davies, Ian Robert, and Dewey, Douglas William, Longmont, CO, for “metadata recovery mechanism for page storage.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A method includes identifying, using a controller, a first data error at a first data block stored in page metadata, the first data block having a first block logical ID. The method also includes identifying a second data block having the first block logical ID. The method also includes copying the second data block to the first data block based on the identified second data block.”

The patent application was filed on November 15, 2018 (16/191,929).

Integrated laser transceiver
Seagate Technology LLC, Fremont, CA, has been assigned a patent (10,895,684) developed by Gubbins, Mark A., Letterkenny, Ireland, Pitwon, Richard C. A., Fareham, Great Britain, Goggin, Aidan D., Redcastle, Ireland, Mooney, Marcus B., Burnfoot, Ireland, Mehfuz, Reyad, Londonderry, Great Britain, El Hallak, Fadi, McElhinney, Paula F., Londonderry, Great Britain, Lafferty, Brendan, Muff, Ireland, and Callan, Kelly E., Londonderry, Great Britain, for an “integrated laser transceiver.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A method, and apparatus provided thereby, includes providing a substrate and placing an integrated laser on the substrate. A first cladding layer surrounds the integrated laser and includes a laser optical coupler aligned with an output of the laser. The laser optical coupler includes silicon and the laser includes a III-V compound semiconductor. The output of the laser is spaced apart from the laser optical coupler by a gap of less than or equal to 500 nanometers. An optical waveguide is positioned on the first cladding layer and in optical communication with the laser optical coupler.”

The patent application was filed on June 21, 2019 (16/449,016).

Fast error recovery with error correction code syndrome weight assist
Seagate Technology LLC, Fremont, CA, has been assigned a patent (10,892,777) developed by Wang, Zheng, Louisville, CO, Patapoutian, Ara, Hopkinton, MA, Goss, Ryan James, Prior Lake, MN, and Khoueir, Antoine, Apple Valley, MN, for a “fast error recovery with error correction code (ECC) syndrome weight assist.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Method and apparatus for decoding error correction code (ECC) code words. Reference voltages are used to extract a selected code word from a communication channel. The selected code word is processed by an ECC decoder, and an initial syndrome weight is determined indicative of unresolved parity errors. A coarse search operates to concurrently adjust, over a first succession of iterations, each of the reference voltages. A subsequent fine search operates, over a second succession of iterations, to individually adjust the reference voltages. Decoding and syndrome weight determination continues over each iteration until a minimum syndrome weight is obtained, after which a user data content of the code word is decoded. The coarse search may transition the decoder from a saturated operational region to a linear operational region. The decoder may be a low density parity check (LDPC) decoder.”

The patent application was filed on February 6, 2019 (16/269,051).

Customized parameterization of read parameters after decoding failure for solid state storage
Seagate Technology LLC, Fremont, CA, has been assigned a patent (10,891,189) developed by Wang, Zheng, Louisville, CO, Patapoutian, Ara, Hopkinton, MA, and Ulriksson, Bengt Anders, Longmont, CO, for a “customized parameterization of read parameters after a decoding failure for solid state storage devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Read parameter estimation techniques are provided that obtain information from multiple read operations to customize read parameters for data recovery. One method comprises performing the following steps, in response to a decoding failure of a page of a memory or a codeword of the memory: obtaining at least three read values of the page or codeword, and processing the at least three read values to determine read parameters comprising: (i) a log likelihood ratio, and/or (ii) a center read reference voltage, wherein the determination is based on a signal count of a number of bits falling in particular regions of multiple regions of the memory and wherein the determined read parameters are used for a decoding of the page or codeword following the decoding failure and/or a subsequent read operation following a successful decoding of the page or codeword.”

The patent application was filed on January 28, 2019 (16/259,346).

Method to fabricate nanochannel for DNA sequencing based on narrow trench patterning process
Seagate Technology LLC, Fremont, CA, has been assigned a patent (10,889,857) developed by Yang, Xiaomin, Livermore, CA, Xiao, ShuaiGang, Fremont, CA, Kuo, David S., Palo Alto, CA, Wago, Koichi, Sunnyvale, CA, and Chang, Thomas Young, Menlo Park, CA, for a “method to fabricate a nanochannel for DNA sequencing based on narrow trench patterning process.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Apparatus and methods relating to DNA sequencing are provided. In one embodiment, a DNA sequencing device includes a nanochannel having a width that is approximately 0.3 nm to approximately 20 nm. A pair of electrodes having portions exposed to the nanochannel may form a tunneling current electrode (TCE) with an electrode gap of approximately 0.1 nm to approximately 2 nm, and more particularly about 0.3 nm to about 1 nm. In one embodiment, at least one of the pair of electrodes is formed as a suspended electrode. An actuator may be associated with the suspended electrode to displace it relative to the other electrode. In various embodiments, the nanochannel and/or the electrodes may be formed using thermal reflow processes to reduce the size of such features.”

The patent application was filed on February 1, 2018 (15/886,533).

Write current switching using effective size of media thermal spot produced by HAMR
Seagate Technology LLC, Fremont, CA, has been assigned a patent (10,885,932) developed by Liu, Xiong, and Li, Quan, Singapore, Singapore, for a “write current switching using an effective size of a media thermal spot produced by a heat-assisted magnetic storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A heat-assisted magnetic recording device includes a write pole positionable adjacent a magnetic recording medium and configured to write data to the medium. A near-field transducer is situated proximate the write pole and configured to produce a thermal spot on the medium. A channel circuit is configured to generate a sequence of symbols having a length of nT, where T is a channel clock rate and n is an integer over a predetermined range. A write driver is configured to apply bi-directional write currents to the write pole to record the sequence of symbols at a location of the thermal spot on the medium, wherein a duration of applying the write currents to the write pole by the write driver is dependent on a length of the sequence of symbols and the effective thermal spot size.”

The patent application was filed on February 24, 2020 (16/798,739).

Allocating part of RAID stripe to repair second RAID stripe
Seagate Technology LLC, Fremont, CA, has been assigned a patent (10,884,889) developed by Luo, Ruiling, Louisville, CO, Davies, Ian, Wicklund, Thomas George, and Dewey, Douglas, Longmont, CO, for an “allocating part of a RAID stripe to repair a second RAID stripe.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Managing a redundant array of independent disks (RAID) storage array involves assigning first and second stripes to span respective first and second sets of disks. A subset of drives in the first set fails such that the first stripe is in a first state wherein a failure of another drive in the first set will lead to data loss in the first stripe. It is determined that the second stripe is in a fault-tolerant state such that the second stripe can have failures of two drives in the second set before the second stripe is in the first state, Part of an operational disk of the second set used by the second stripe is allocated to the first stripe to replace at least part of the subset of failed drives.”

The patent application was filed on June 22, 2018 (16/016,012).