SanDisk/Western Digital Assigned Eighteen Patents

Three-dimensional memory device containing eye-shaped contact via structures located in laterally-undulating trenches
SanDisk Technologies LLC, (acquired by Western Digital Corp.), Addison, TX, has been assigned a patent (10,985,176) developed by Iwai, Takaaki, Otsu, Yoshitaka, and Otoi, Hisakazu, Yokkaichi, Japan, for “three-dimensional memory device containing eye-shaped contact via structures located in laterally-undulating trenches and method of making the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers located over a semiconductor material layer, and memory stack structures extending through one of the alternating stacks. Laterally-undulating backside trenches are present between alternating stacks, and include a laterally alternating sequence of straight trench segments and bulging trench segments. Cavity-containing dielectric fill structures and contact via structures are present in the laterally-undulating backside trenches. The contact via structures are located within the bulging trench segments. The contact via structures are self-aligned to sidewalls of the alternating stacks. Additional contact via structures may vertically extend through a dielectric alternating stack of a subset of the insulating layers and dielectric spacer layers laterally adjoining one of the alternating stacks.”

The patent application was filed on March 27, 2019 (Appl. No.16/366,330).

Three-dimensional memory with mobility-enhanced vertical channels
SanDisk Technologies LLC, (acquired by Western Digital Corp.), Addison, TX, has been assigned a patent (10,985,172) developed by Ge, Chun, Zhang, Yanli, Zhou, Fei, San Jose, CA, and Makala, Raghuveer S., Campbell, CA, for “three-dimensional memory device with mobility-enhanced vertical channels and methods of forming the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A combination of an alternating stack and a memory opening fill structure is provided over a substrate. The alternating stack includes insulating layers and electrically conductive layers. The memory opening fill structure vertically extends through the alternating stack, and includes a memory film, a vertical semiconductor channel, and a core structure comprising a core material. A phase change material is employed for the core material. A volume expansion is induced in the core material by performing an anneal process that induces a microstructural change within the core material. The volume expansion in the core material induces a lateral compressive strain and a vertical tensile strain within the vertical semiconductor channel. The vertical tensile strain enhances charge mobility in the vertical semiconductor channel, and increases the on-current of the vertical semiconductor channel.”

The patent application was filed on January 18, 2019 (Appl. No.16/251,854).

Three-dimensional flat NAND memory including wavy word lines
SanDisk Technologies LLC, (acquired by Western Digital Corp.), Addison, TX, has been assigned a patent (10,985,171) developed by Kaneko, Ryosuke, Yokkaichi, Japan, for “three-dimensional flat NAND memory device including wavy word lines and method of making the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips located over a substrate, generally extending along a first horizontal direction, and laterally spaced apart from each other along a second horizontal direction by width-modulated line trenches, memory films located on a respective sidewall of the alternating stacks, generally extending along the first horizontal direction, and laterally undulating along the second horizontal direction, and a plurality of discrete vertical semiconductor channels located on a sidewall of a respective one of the memory films.”

The patent application was filed on September 26, 2018 (Appl. No.16/142,447).

Three-dimensional device with bonded structures including support die
SanDisk Technologies LLC, (acquired by Western Digital Corp.), Addison, TX, has been assigned a patent (10,985,169) developed by Kai, James, Santa Clara, CA, Chowdhury, Murshed, Fremont, CA, Matsuno, Koichi, and Alsmeier, Johann, San Jose, CA, for “three-dimensional device with bonded structures including a support die and methods of making the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory die including a three-dimensional array of memory elements and a logic die including a peripheral circuitry that support operation of the three-dimensional array of memory elements can be bonded by die-to-die bonding to provide a bonded assembly. External bonding pads for the bonded assembly can be provided by forming recess regions through the memory die or through the logic die to physically expose metal interconnect structures within interconnect-level dielectric layers. The external bonding pads can include, or can be formed upon, a physically exposed subset of the metal interconnect structures. Alternatively or additionally, laterally-insulated external connection via structures can be formed through the bonded assembly to multiple levels of the metal interconnect structures. Further, through-dielectric external connection via structures extending through a stepped dielectric material portion of the memory die can be physically exposed, and external bonding pads can be formed thereupon.”

The patent application was filed on March 4, 2019 (Appl. No.16/291,577).

Differential dbus scheme for low-latency random read for NAND memories
SanDisk Technologies LLC, (acquired by Western Digital Corp.), Addison, TX, has been assigned a patent (10,984,874) developed by Yabe, Hiroki, Hayashi, Koichiro, Ariki, Takuya, Ookuma, Naoki, and Miwa, Toru, Kanagawa, Japan, for a “differential dbus scheme for low-latency random read for NAND memories.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A random access memory is provided including a plane structure comprising a plurality of sense amplifiers, each including a local data latch, a pair of local busses connected to each of the data latches, a differential data bus, and a pair of redrivers connected between the pair of local busses and the differential data bus.”

The patent application was filed on November 13, 2019 (Appl. No.16/681,968).

Ferroelectric memory device with select gate transistor
SanDisk Technologies LLC, (acquired by Western Digital Corp.), Addison, TX, has been assigned a patent (10,978,482) developed by Alsmeier, Johann, and Zhang, Yanli, San Jose, CA, for “ferroelectric memory device with select gate transistor and method of forming the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory cell includes a ferroelectric memory transistor, and a select gate transistor which shares a common semiconductor channel, a common source region and a common drain region with the ferroelectric memory transistor. The select gate transistor controls access between the common source region and the common semiconductor channel.”

The patent application was filed on June 28, 2019 (Appl. No.16/456,736).

Mitigating grown bad blocks
SanDisk Technologies LLC, (acquired by Western Digital Corp.), Addison, TX, has been assigned a patent (10,978,160) developed by Wu, Jianzhi, Milpitas, CA, Yang, Xiang, Santa Clara, CA, and Wan, Jun, San Jose, CA, for “mitigating grown bad blocks.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Example techniques that mitigate against memory hole shorts during an erase operation for memory cells in a string include an example method in which, during an erase operation, erase pulses are applied to the word lines of the memory string and terminated at different times based. In some instances, the erase pulses applied to the word lines of the memory string are terminated based on the temperature of the memory cells of the memory string. In further implementations, the erase pulses applied to the word lines of the memory string are boosted for different times depending on the location of the word line along the memory string during the erase operation.”

The patent application was filed on December 31, 2018 (Appl. No.16/236,792).

Concurrent programming of multiple cells for non-volatile memory
SanDisk Technologies LLC, (acquired by Western Digital Corp.), Addison, TX, has been assigned a patent (10,978,156) developed by Yang, Xiang, Lee, Aaron, Hemink, Gerrit Jan, Oowada, Ken, and Miwa, Toru, San Jose, CA, for a “concurrent programming of multiple cells for non-volatile memory devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Apparatuses, systems, and methods are disclosed for concurrently programming non-volatile storage cells, such as those of an SLC NAND array. The non-volatile storage cells may be arranged into a first block comprising a first string of storage cells that intersects with a first word line at a first storage cell, a second block comprising a second string of storage cells that intersects with a second word line at a second storage cell, a bit line electrically connectable to the first string and the second string, and controller configured to apply a programming pulse, at an elevated voltage, to the first word line and second word line to concurrently program the first and second storage cells.”

The patent application was filed on June 29, 2018 (Appl. No.16/024,002).

Adaptive VPASS for 3D flash memory with pair string structure
SanDisk Technologies LLC, (acquired by Western Digital Corp.), Addison, TX, has been assigned a patent (10,978,152) developed by Gautam, Rajdeep, Yokohama, Japan, Chibvongodze, Hardwell, Hiratsuka, Japan, and Oowada, Ken, Fujisawa, Japan, for an “adaptive VPASS for 3D flash memory with pair string structure.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Systems and methods for reducing program disturb when programming portions of a memory array are described. A memory array may include a first set of NAND strings and a second set of NAND strings that share a common bit line that is connected to the drain-side end of drain-side select gates of the NAND strings and/or share a common source-side select gate line that connects to the gates of source-side select gates of the NAND strings. During programming of the first set of NAND strings a first pass voltage (e.g., 7V) may be applied to unselected word lines of the memory array and subsequently during programming of the second set of NAND strings a second pass voltage (e.g., 9V) greater than the first pass voltage may be applied to the unselected word lines of the memory array.”

The patent application was filed on November 13, 2019 (Appl. No.16/682,730).

Dynamic bit-scan techniques for memory device programming
SanDisk Technologies LLC, (acquired by Western Digital Corp.), Addison, TX, has been assigned a patent (10,971,222) developed by Lin, Lei, Fremont, CA, Li, Zhuojie, Newark, CA, Chin, Henry, Fremont, CA, and Hsu, Cynthia, Milpitas, CA, for a “dynamic bit-scan techniques for memory device programming.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”An apparatus is provided that includes a plurality of memory cells, a programming circuit configured to apply a plurality of programming pulses to the memory cells, and a scanning circuit configured to repeatedly switch between performing an n-state bitscan after each programming pulse until first predetermined criteria are satisfied, and performing an m-state bitscan after each programming pulse until second predetermined criteria are satisfied, where m>n, and n>0.”

The patent application was filed on December 17, 2019 (Appl. No.16/717,532).

VHSA-VDDSA generator merging scheme
SanDisk Technologies LLC, (acquired by Western Digital Corp.), Addison, TX, has been assigned a patent (10,971,209) developed by Kwon, Ohwon, Tei, Kou, and G, VSNK Chaitanya, San Jose, CA, for a “VHSA-VDDSA generator merging scheme.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory device is provided including physical block circuitry including a first lateral network arrangement and a second lateral network arrangement. Each of the first and second lateral network arrangements includes a single generator configured to output both a sense amplifier voltage VHSA and a data latch voltage VDDSA, in each of a first mode and a second mode. In the first mode, during which read and program verify and other operations may occur, the generator receives VHSA as a feedback signal and in the second mode, during which programming, POR, and EVFY operations may occur, the generator receives VDDSA as a feedback signal.”

The patent application was filed on October 4, 2019 (Appl. No.16/593,576).

Low latency data transfer
SanDisk Technologies LLC, (acquired by Western Digital Corp.), Addison, TX, has been assigned a patent (10,971,202) developed by Chen, Chen, Mountain View, CA, Li, Yenlung, and, Peng, Min, San Jose, CA, for a “low latency data transfer.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Apparatuses and techniques are described for transferring data out of a memory device with low latency. Data can be stored in data transfer latches for NAND strings arranged in columns in divisions of a block. Data can be output from the data transfer latches for different columns in different divisions in each transfer. For example, the data output can include data from an nth column in some divisions and an n+1.sup.st column in other divisions. This avoids outputting unwanted data at the start of a data transfer. The data from the data transfer latches is output to a data pipeline and then to a set of control latch circuits. The data can be clocked out from a last control latch circuit of the set in a desired division order by use of separate multiplexer control signals for the control latch circuits.”

The patent application was filed on April 15, 2020 (Appl. No.16/849,827).

Microcontroller for non-volatile memory with combinational logic
SanDisk Technologies LLC, (acquired by Western Digital Corp.), Addison, TX, has been assigned a patent (10,971,199) developed by Koh, Pao-Ling, Fremont, CA, Zhang, Yuheng, Saratoga, CA, and Li, Yan, Milpitas, CA, for a “microcontroller for non-volatile memory with combinational logic.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit is configured to control the non-volatile memory structure to perform memory operations by generating and applying a set of control signals to the non-volatile memory structure The control circuit includes a programmable and reprogrammable microcontroller. For example, the microcontroller includes one or more processors that are programmed using software, e.g., firmware). The use of a programmable processor and software allows for updates and changes to be made easily. Additionally, to reduce the time taken to make some calculations, the microcontroller also includes one or more combinational logic circuits that are in communication with the one or more processors.”

The patent application was filed on June 20, 2019 (Appl. No.16/446,705).

Three-dimensional memory containing channels with laterally pegged dielectric cores
SanDisk Technologies LLC, (acquired by Western Digital Corp.), Addison, TX, has been assigned a patent (10,964,715) developed by Kakazu, Manabu, Yuda, Takashi, and Fukano, Yuji, Yokkaichi, Japan, for a “three-dimensional memory device containing channels with laterally pegged dielectric cores.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A three-dimensional memory device includes a vertical semiconductor channel surrounding a vertical dielectric core. Laterally extending dielectric pegs structurally support the vertical semiconductor channel and the vertical dielectric core. The vertical semiconductor channel may be a single crystalline semiconductor channel.”

The patent application was filed on February 5, 2019 (Appl. No.16/268,132).

Reprogramming memory cells to tighten threshold voltage distributions and improve data retention
SanDisk Technologies LLC, (acquired by Western Digital Corp.), Addison, TX, has been assigned a patent (10,964,402) developed by Chen, Han-Ping, Santa Clara, CA, Chin, Henry, Fremont, CA, and Baraskar, Ashish, Santa Clara, CA, for “reprogramming memory cells to tighten threshold voltage distributions and improve data retention.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Techniques are described for reprogramming memory cells to tighten threshold voltage distributions and improve data retention. In one aspect, the memory cells of a word line WLn are reprogrammed after programming of memory cells of an adjacent, later-programmed word line WLn+1. The reprogramming can be limited to lower state memory cells of WLn which are adjacent to lower state memory cells of WL+1. A program pulse magnitude used in the reprogramming can be tailored to the data states of the WLn memory cell and the adjacent, WLn+1 memory cell. In some cases, the program pulse magnitudes can be grouped to reduce the implementation complexity and time. The reprogramming can occur after an initial program operation has completed, during an idle time of a control circuit.”

The patent application was filed on February 19, 2020 (Appl. No.16/794,614).

Ferroelectric device with multiple polarization states
SanDisk Technologies LLC, (acquired by Western Digital Corp.), Addison, TX, has been assigned a patent (10,957,711) developed by Prasad, Bhagwati, and Kalitsov, Alan, San Jose, CA, for “ferroelectric device with multiple polarization states and method of making the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A ferroelectric device includes a semiconductor channel region, a gate electrode, and a ferroelectric gate dielectric located between the channel region and the gate electrode, and including a plurality of ferroelectric gate dielectric portions having different structural defect densities.”

The patent application was filed on January 31, 2020 (Appl. No.16/778,245).

Multi-tier three-dimensional memory with dielectric support pillars
SanDisk Technologies LLC, (acquired by Western Digital Corp.), Addison, TX, has been assigned a patent (10,957,706) developed by Otsu, Yoshitaka, Nozawa, Kei, Doda, Yashushi, Hojo, Naoto, Tanaka, Yoshinobu, and Ito, Koichi, Yokkaichi, Japan, for “multi-tier three-dimensional memory device with dielectric support pillars and methods for making the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A multi-tier three-dimensional memory array includes multiple alternating stacks of insulating layers and electrically conductive layers that are vertically stacked. Memory stack structures including memory films and semiconductor channels extend through the alternating stacks. The alternating stacks are formed as alternating stacks of insulating layers and sacrificial material layers, and are subsequently modified by replacing the sacrificial material layers with electrically conductive layers. Structural support during replacement of the sacrificial material layers with the electrically conductive layers is provided by the memory stack structures and dielectric support pillar structures. The dielectric support pillar structures may be formed only for a first-tier structure including a first-tier alternating stack of first insulating layers and first spacer material layers, or may vertically extend over multiple tiers. The dielectric support pillar structures may be formed before or after formation of stepped surfaces in the alternating stack.”

The patent application was filed on February 15, 2019 (Appl. No.16/276,952).

Three-dimensional memory having multi-stack bonded structure using logic die and multiple three-dimensional memory dies
SanDisk Technologies LLC, (acquired by Western Digital Corp.), Addison, TX, has been assigned a patent (10,957,705) developed by Totoki, Yuji, Inoue, Shigehisa, Kasai, Yuki, and Matsuoka, Hironori, Yokkaichi, Japan, for “three-dimensional memory devices having a multi-stack bonded structure using a logic die and multiple three-dimensional memory dies and method of making the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A first memory die including an array of first memory stack structures and a logic die including a complementary metal oxide semiconductor (CMOS) circuit are bonded. The CMOS circuit includes a first peripheral circuitry electrically coupled to nodes of the array of first memory stack structures through a first subset of first metal interconnect structures included within the first memory die. A second memory die is bonded to the first memory die. The second memory die includes an array of second memory stack structures. The CMOS circuit includes a second peripheral circuitry electrically coupled to nodes of the array of second memory stack structures through a second subset of first metal interconnect structures included within the first memory die and through second metal interconnect structures included within the second memory die. The logic die provides peripheral devices that support operation of memory stack structures in multiple memory dies.”

The patent application was filed on December 24, 2018 (Appl. No.16/231,752).