Yangtze Memory Technologies Assigned Four Patents

Programming memory
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (10,943,650) developed by Liang, Ke, Hou, Chun Yuan, and Tang, Qiang, Wuhan, China, for a “method for programming memory system.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory system comprising a plurality of memory cells each including a storage element having a first terminal and a control terminal. The method for operating the memory system includes applying a first program voltage to control terminals of storage elements and applying a basic reference voltage to first terminals of the storage elements during a first program operation, performing a group verification by comparing threshold voltages of the storage elements with a middle voltage, performing a first program test to check if the threshold voltages of the storage elements are greater than a first programming threshold voltage, and performing a second program operation according to a result of the group verification and a result of the first program test. The middle voltage is smaller than the first programming threshold voltage.”

The patent application was filed on May 12, 2019 (16/409,855).

Three-dimensional memory with three-dimensional phase-change memory
Yangtze Memory Technologies Co., Ltd., Hubei, China, has been assigned a patent (10,937,766) developed by Liu, Jun, Wuhan, China, for a “three-dimensional memory device with three-dimensional phase-change memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Embodiments of three-dimensional (3D) memory devices with 3D phase-change memory (PCM) and methods for forming and operating the 3D memory devices are disclosed. In an example, a 3D memory device includes a first semiconductor structure including a peripheral circuit, an array of 3D PCM cells, and a first bonding layer including a plurality of first bonding contacts. The 3D memory device also further includes a second semiconductor structure including an array of 3D NAND memory strings and a second bonding layer including a plurality of second bonding contacts. The 3D memory device further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.”

The patent application was filed on October 30, 2019 (16/669,454).

Programming multilevel cell NAND flash memory and MLC NAND flash memory
Yangtze Memory Technologies Co., Ltd., Hubei, China, has been assigned a patent (10,937,514) developed by Wan, Wei Jun, Wuhan, China, for a “method of programming multilevel cell NAND flash memory device and MLC NAND flash memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A method of programming a NAND flash memory device includes: a programming voltage generation circuit applying an initial programming voltage pulse to a predetermined page of NAND flash memory, a controller verifying a plurality of verification levels of the predetermined page, the plurality of verification levels being less than a first-state verification voltage of verifying a lowest program state of the predetermined page, the controller determining a magnitude of a subsequent programming voltage pulse upon one of the plurality of verification levels of the predetermined page passing a verification, and the programming voltage generation circuit applying the subsequent programming voltage pulse to the predetermined page.”

The patent application was filed on July 16, 2019 (16/513,658).

Interconnect structure of three-dimensional memory
Yangtze Memory Technologies Co., Ltd., Hubei, China, has been assigned a patent (10,930,663) developed by Lu, Zhenyu, Song, Lidong, Li, Yongna, Pan, Feng, Yang, Steve Weiyi, and Shi, Wenguang, Hubei, China, for an “interconnect structure of three-dimensional memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Embodiments of interconnect structures of a three-dimensional, 3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a substrate, an alternating layer stack including a staircase structure on the substrate, and a barrier structure extending vertically through the alternating layer stack. The alternating layer stack includes an alternating dielectric stack and an alternating conductor/dielectric stack. The alternating dielectric stack includes dielectric layer pairs enclosed by at least the barrier structure. The alternating conductor/dielectric stack includes conductor/dielectric layer pairs. The memory device further includes a channel structure and a slit structure each extending vertically through the alternating conductor/dielectric stack, an etch stop layer on an end of the channel structure, and first contacts. Each of a conductor layer of the alternating conductor/dielectric stack in the staircase structure, the etch stop layer, and the slit structure is in contact with one of the first contacts.”

The patent application was filed on July 26, 2018 (16/046,873).