MemRay and Yonsei University, University-Industry Foundation Assigned Two Patents

Memory controlling
MemRay Corporation, Seoul, Korea, and Yonsei University, University-Industry Foundation, UIF, Seoul, Korea, has been assigned a patent (10,929,291) developed by Jung, Myoungsoo, Gouk, Donghyun, Kwon, Miryeong, Koh, SungJoon, and Zhang, Jie, Incheon, Korea, for “memory controlling device and computing device including the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory controlling device of a computing device including a CPU, a memory, and a flash-based storage device is provided. The memory controlling device includes an address manager and an interface. The address manager aggregates a memory space of the memory and a storage space of the storage device into an expanded memory space, and handles a memory request for the expanded memory space from the CPU by using the memory space of the memory as a cache for the storage space of the storage device. The interface is used to access the memory and the storage device.”

The patent application was filed on November 23, 2018 (16/198,972).

Memory controlling including phase change memory
MemRay Corporation, Seoul, Korea, and Yonsei University, University-Industry Foundation, UIF, Seoul, Korea, has been assigned a patent (10,929,284) developed by Jung, Myoungsoo, and Park, Gyuyoung, Incheon, Korea, for “memory controlling device including phase change memory and memory system including the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory system including a memory subsystem and a memory controller is provided. The memory subsystem includes a plurality of first memory modules implemented by a phase-change memory and a second memory module implemented by a memory whose write speed is faster than that of the phase-change memory. The memory controller generates a non-blocking code from a plurality of sub-data into which original data are divided, writes the non-blocking code to the second memory module, writes the plurality of sub-data to the plurality of first memory modules, respectively, and reconstructs the original data from some sub-data of the plurality of sub-data which are read from some of the plurality of first memory modules and the non-blocking code read from the second memory under a predetermined condition at a read request.”

The patent application was filed on August 16, 2019 (16/542,346).