With Anritsu, Tektronix Introduces PCIe 5.0 Transceiver and Reference Clock Solution

Tektronix, Inc. in collaboration with Anritsu Corp., introduced a PCIe 5.0 transceiver (Base and CEM) and reference clock solution, becoming the first company to offer early CEM fixtures for pre-compliance testing.

This collaboration enables industry-receiver verification, complementing a transmitter and reference clock test suite.

PCIe continues to extend its industry leadership as the dominant high-speed serial computer bus by doubling bandwidth every 3 years and exceeding the target with the introduction of the 5.0 Base spec (128GB/s). This rapid development pace is expected to continue as PCI-SIG, the standard-setting body for peripheral component I/O data transfers, announced the PCIe 6.0 spec (256GB/s) to be delivered in 2021 and include multi-level PAM4 signaling.

“As the first company to offer CEM testing fixtures for PCIe Gen5, we are proud to help our customers once again speed the pace of innovation, giving them a leg up on competition,” says Chris Witt, VP and GM, Tektronix.

The server/storage industry is rapidly transitioning to PCIe 5.0 due to new requirements imposed by 400GbE, cloud AI and modeling (co-processors), storage capacity, and NAND-based storage. This rapid progression brings a new problem set for test and measurement traditionally split into Base silicon level validation and CEM compliance testing with the PCI-SIG.

“Electronics designers today demand future-proofing to protect their innovations’ longevity into tomorrow,” says Takeshi Shima, SVP, Anritsu. “Providing a solution through Gen6 gives our customers a sense of our commitment to stay with them on the cutting edge of development.“

“As PCIe becomes faster and more complex with the emergence of the Gen5 standard, engineers are faced with new design challenges, shorter time-to-market windows, new standards specs to understand and apply, and new compliance testing requirements,” says David Bouse, PCIe systems engineer, Tektronix. “It is vital to have a comprehensive test equipment and software solution in place prior to workshop certification. Our PCIe 5.0 test and debug solution can easily guide the engineer through compliance testing and debug to ensure their design meets new standards with a high degree of confidence.“

The PCIe 5.0 transceiver and reference clock solution was developed and continues to be aligned with the 5.0 Base spec, 5.0 CEM spec, and 5.0 test specs.

Key features include:

• PCIe 5.0 (32GT/s) automated Base and CEM transceiver solution running on DPO700000SX series 70GHz real time oscilloscope and MP1900A Signal Quality Analyzer-R series (BERT) from Anritsu

• Receiver automation software from Tektronix with highly efficient algorithms for stressed eye calibration at 32GT/s and 16GT/s

• Tool support including SigTest Phoenix with highly parallelized processing to reduce overall test time

• Multiple form factors (M.2 and U.2) and clocking architectures (CC, SRNS, SRIS)

• Follows real time evolution of the 5.0 Base spec with 32GT/s uncorrelated jitter and pulse width jitter measurements implemented to optimize A/D range and minimize noise

• Addresses the increasing challenges of 100MHz reference clock jitter and signal integrity measurements through full integration with the Silicon Labs ‘PCIe Clock Jitter’ tool and Tektronix’s DPOJET tool

• First pre-compliance test fixtures for PCIe 5.0 CEM testing

The Tektronix PCIe solution is available worldwide for use with DPO/MSO70000SX/DX.