Kioxia and Western Digital Unveils 162-Layer 3D Flash Memories

Kioxia Corporation and Western Digital Corp. developed their sixth-gen, 162-layer 3D flash memory technology.

Sixth-gen 3D flash memory

Marking the next milestone in the companies’ 20-year joint-venture partnership, this is the companies’ highest density and most advanced 3D flash memory technology to date, utilizing a range of technology and manufacturing innovations.

“Through our strong partnership that has spanned two decades, Kioxia and Western Digital have successfully created unrivaled capabilities in manufacturing and R&D,” said Masaki Momodomi, CTO, Kioxia. “Together, we produce over 30% ⁽¹⁾ of the world’s flash memory bits and are steadfast in our mission to provide exceptional capacity, performance and reliability at a compelling cost. We each deliver this value proposition across a range of data-centric applications from personal electronics to data centers as well as emerging applications enabled by 5G networks, AI and autonomous systems.“

Beyond vertical scaling – New architecture leverages innovations
“As Moore’s Law reaches its physical limits across the semiconductor industry, there’s one place where Moore’s Law continues its relevancy – that’s in flash,” said Dr. Siva Sivaram, president, technology and strategy, Western Digital. “To continue these advances and meet the world’s growing data demands, a new approach to 3D flash memory scaling is critical. With this new gen, Kioxia and Western Digital are introducing innovations in vertical as well as lateral scaling to achieve greater capacity in a smaller die with fewer layers. This innovation ultimately delivers the performance, reliability and cost that customers need.“

This sixth-gen 3D flash memory features architecture beyond conventional eight-stagger memory hole array and achieves up to 10% greater lateral cell array density compared to the fifth-gen technology. This lateral scaling advancement, in combination with 162 layers of stacked vertical memory, enables a 40% reduction in die size compared to the 112-layer stacking technology, optimizing cost.

The 3 companies teams also applied Circuit Under Array CMOS placement and 4-plane operation, which together deliver nearly 2.4x improvement in program performance and 10% in read latency compared to the previous gen. I/O performance also improves by 66%, enabling the next-gen interface to support the increasing need for faster transfer rates.

Overall, this 3D flash memory technology reduces the cost per bit, as well as increases the manufactured bits per wafer by 70%, compared with the previous gen.

The companies detailed the related innovations in a joint presentation at the ISSCC 2021 show.

⁽¹⁾ Source: As of February 18, 2021, Kioxia survey