Xilinx Assigned Patent

Xilinx, Inc., San Jose, CA, has been assigned a patent (10,861,578) developed by Flateau, Jr., Roger D., and Knopp, Tomai, San Jose, CA, for a “distributed memory repair network.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A device includes a plurality of memory components with redundant columns associated therewith, a sub-block controller, and a volatile memory. The sub-block controller generates a repair vector, during manufacture testing mode. The repair vector is associated with the plurality of memory components and is generated responsive to detecting a defect within a column of the plurality of memory components. No repair vector is generated responsive to detecting no defect within a column of the plurality of memory components. The volatile memory receives and stores the repair vector in a nonvolatile memory component, during the manufacture testing mode. The volatile memory receives the repair vector from the nonvolatile memory component if the repair vector was generated during the manufacture testing mode, at startup mode, and provides it to the sub-block controller. The sub-block controller loads a repair data into the plurality of memory components based on the repair vector.”

The patent application was filed on December 18, 2019 (16/718,535).