SanDisk/WD Assigned Sixteen Patents

Phase change memory
SanDisk Technologies LLC, a Western Digital Corp. company, Addison, TX, has been assigned a patent (10,868,245) developed by Bai, Zhaoqiang, Apodaca, Mac, Grobis, Michael, Tran, Michael Nicolas Albert, San Jose, CA, Robertson, Neil Leslie, Palo Alto, CA, and Bertero, Gerardo, Redwood City, CA, for a “phase change memory device with crystallization template and method of making the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A phase change memory device includes a phase change material portion located between a first electrode and a second electrode, and a crystallization template material portion located between the first electrode and the second electrode in contact with the phase change material portion. The crystallization template material portion and the phase change material portion belong to a same crystal system and have matching lattice spacing, or the crystallization template material portion and the phase change material portion do not belong to the same crystal system, but have a matching translational symmetry along at least one paired lattice plane with a matching lattice spacing.”

The patent application was filed on June 5, 2019 (16/432,356).

Ferroelectric memory
SanDisk Technologies LLC, a Western Digital Corp. company, Addison, TX, has been assigned a patent (10,868,042) developed by Zhang, Yanli, and Alsmeier, Johann, San Jose, CA, for a “ferroelectric memory device containing word lines and pass gates and method of forming the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory device includes a semiconductor channel extending between a source region and a drain region, a plurality of pass gate electrodes, a plurality of word lines, a gate dielectric located between the semiconductor channel and the plurality of pass gate electrodes, and ferroelectric material portions located between the semiconductor channel and the plurality of word lines.”

The patent application was filed on June 28, 2019 (16/457,687).

Three-dimensional memory
SanDisk Technologies LLC, a Western Digital Corp. company, Addison, TX, has been assigned a patent (10,868,025) developed by Zhou, Fei, San Jose, CA, Rajashekhar, Adarsh, Santa Clara, CA, Sharangpani, Rahul, Fremont, CA, and Makala, Raghuveer S., Campbell, CA, for a “three-dimensional memory device including replacement crystalline channels and methods of making the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”In-process source-level material layers including a source-level sacrificial layer are formed over a substrate. An alternating stack of insulating layers and sacrificial material layers is formed over the in-process source-level material layers. A memory opening is formed through the alternating stack, and is filled with a memory film and a sacrificial opening fill structure. The source-level sacrificial layer is replaced with a source contact layer including a doped polycrystalline semiconductor material. The source contact layer can be formed by diffusing a metal in a metallic catalyst material through a semiconductor fill material layer that fills a source cavity formed by removal of the source-level sacrificial layer. The sacrificial opening fill structure is replaced with a vertical semiconductor channel, which can be formed with large grains due to large crystal sizes in the source contact layer. The sacrificial material layers are replaced with electrically conductive layers.”

The patent application was filed on November 26, 2018 (16/200,115).

Computer-readable media for managing instruction fetch in virtual computing environments
SanDisk Technologies LLC, a Western Digital Corp. company, Addison, TX, has been assigned a patent (10,866,910) developed by Benisty, Shay, Beer Sheva, Israel, and Koul, Rajesh, San Jose, CA, for “systems, methods, and computer-readable media for managing instruction fetch in virtual computing environments.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Methods, systems, and computer readable media for intelligent fetching of storage device commands from submission queues are disclosed. The controller may implement a hierarchical scheme comprising first-level arbitration(s) between submission queues of each of a plurality of input/output virtualization (IOV) functions, and a second-level arbitration between the respective IOV functions. Alternatively, or in addition, the controller may implement a flat arbitration scheme, which may comprise selecting submission queue(s) from one or more groups, each group comprising submission queues of each of the plurality of IOV functions. In some embodiments, the controller implements a credit-based arbitration scheme. The arbitration scheme(s) may be modified in accordance with command statistics and/or current resource availability.”

The patent application was filed on March 26, 2018 (15/936,364).

Spin-transfer torque MRAM
SanDisk Technologies LLC, a Western Digital Corp. company, Addison, TX, has been assigned a patent (10,862,022) developed by Le, Quang, San Jose, CA, Li, Zhanjie, Pleasanton, CA, Bai, Zhigang, Fremont, CA, Vanderheijden, Paul, Cupertino, CA, and Ho, Michael, Redwood City, CA, for a “spin-transfer torque MRAM with magnetically coupled assist layers and methods of operating the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A MRAM device includes a magnetic tunnel junction containing a reference layer having a fixed magnetization direction, a free layer, and a nonmagnetic tunnel barrier layer located between the reference layer and the free layer, a first magnetic assist layer, a second magnetic assist layer, an antiferromagnetic coupling spacer layer located between the first and second magnetic assist layers, and a first nonmagnetic spacer layer located between the free layer and the first magnetic assist layer. The antiferromagnetic coupling spacer layer is configured to provide antiferromagnetic coupling between a first magnetization direction of the first magnetic assist layer and a second magnetization direction of the second magnetic assist layer.”

The patent application was filed on December 6, 2018 (16/212,342).

Three-dimensional memory
SanDisk Technologies LLC, a Western Digital Corp. company, Addison, TX, has been assigned a patent (10,861,873) developed by Kim, Jee-Yeon, San Jose, CA, Kim, Kwang-Ho, Pleasanton, CA, and Toyama, Fumiaki, Cupertino, CA, for a “three-dimensional memory device including signal and power connection lines extending through dielectric regions and methods of making the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A three-dimensional memory device includes a plurality of alternating stacks of insulating layers and electrically conductive layers located over a substrate, clusters of memory stack structures vertically extending through a respective one of the alternating stacks, and bit lines electrically connected to an upper end of a respective subset of the vertical semiconductor channels. In one embodiment, a subset of the bit lines can include a respective multi-level structure. Each multi-level structure includes bit-line-level bit line segments and an interconnection line segment located at a different level from the bit-line-level bit line segments. In another embodiment, groups of alternating stacks can be alternately indented along a horizontal direction perpendicular to the bit lines to provide dielectric material portions located in lateral indentation regions. Metal line structures connecting contact via structures can extend parallel to bit lines to provide electrical connections between word lines and underlying field effect transistors.”

The patent application was filed on May 7, 2019 (16/404,844).

Three-dimensional memory array
SanDisk Technologies LLC, a Western Digital Corp. company, Addison, TX, has been assigned a patent (10,861,871) developed by Tobioka, Akihiro, Nagoya, Japan, for a “three-dimensional memory array including self-aligned dielectric pillar structures and methods of making the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”An alternating stack of insulating layers and spacer material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. A pair of backside trenches and a set of nested trenches are simultaneously formed through the alternating stack. Each trench within the set of nested trenches is spaced from any other trench within the set of nested trenches by at least one patterned remaining portion of the alternating stack having a respective shape of an enclosing wall. The at least one patterned remaining portion of the alternating stack is removed from inside to outside using sequential etch processes. A dielectric pillar structure is formed within the pillar-shaped cavity. The sacrificial material layers are replaced with electrically conductive layers. A through-memory-level conductive via structure is formed through the dielectric pillar structure.”

The patent application was filed on March 14, 2019 (16/353,048).

Three-dimensional memory
SanDisk Technologies LLC, a Western Digital Corp. company, Addison, TX, has been assigned a patent (10,861,869) developed by Nakamura, Ryo, Ueda, Yu, Hinoue, Tatsuya, Inoue, Shigehisa, Mizuno, Genta, and Tsutsumi, Masanori, Yokkaichi, Japan, for a “three-dimensional memory device having a slimmed aluminum oxide blocking dielectric and method of making same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Each of the memory stack structures includes respective charge storage elements and a respective vertical semiconductor channel contacting an inner sidewall of the respective charge storage elements. The sacrificial material layers are replaced with electrically conductive layers. A polycrystalline aluminum oxide blocking dielectric layer is provided between each charge storage element and a neighboring one of the electrically conductive layers. The polycrystalline aluminum oxide blocking dielectric layer is formed by: depositing an amorphous aluminum oxide layer, converting the amorphous aluminum oxide layer into an in-process polycrystalline aluminum oxide blocking dielectric layer, and by thinning the in-process polycrystalline aluminum oxide blocking dielectric layer.”

The patent application was filed on January 8, 2019 (16/242,245).

Controlled string erase for nonvolatile memory
SanDisk Technologies LLC, a Western Digital Corp. company, Addison, TX, has been assigned a patent (10,861,559) developed by Desai, Amul, Milpitas, CA, and Pachamuthu, Jayavel, San Jose, CA, for “controlled string erase for nonvolatile memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A methodology and structure for selectively erases a group of strings in a vertical NAND memory array to account for the slow to erase memory cells in the inner strands compared to the outer strands in the group. Erase signals can be applied through both the drain side connections and the source side connections in a first step to erase the outer strings. A second erase signal can be applied to the inner strands to erase the inner strands. The second signal can be applied from just the drain side connections or through both the drain side connections and the source side connections. In another embodiment, the erase signals are applied from both the source side connections and the drain side connections to the inner strings and only from the source side connections to the outer strings.”

The patent application was filed on December 20, 2019 (16/722,322).

Three-dimensional memory
SanDisk Technologies LLC, a Western Digital Corp. company, Addison, TX, has been assigned a patent (10,854,629) developed by Ge, Chun, Fremont, CA, Yu, Jixin, Milpitas, CA, Yu, Fabo, San Ramon, CA, Li, Xin Yuan, Yokkaichi, Japan, and Zhang, Yanli, San Jose, CA, for a “three-dimensional memory device containing asymmetric, different size support pillars and method for making the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”An alternating stack of insulating layers and spacer material layers is formed over a substrate. A staircase region having stepped surfaces is formed by patterning the alternating stack. Memory opening fill structures are formed in a memory array region, and support pillar structures are formed in the staircase region. Each of the memory stack structures includes a memory film and a vertical semiconductor channel. The support pillar structures include first support pillar structures and having a first maximum lateral dimension and second support pillar structures having a second maximum lateral dimension that is less than the first maximum lateral dimension and interlaced with the first support pillar structures. The sacrificial material layers are replaced with electrically conductive layers. The second support pillar structures are positioned interstitially among the first support pillar structures and contact via structures that are formed on the electrically conductive layers to provide additional structural support.”

The patent application was filed on March 28, 2019 (16/368,007).

Three-dimensional memory
SanDisk Technologies LLC, a Western Digital Corp. company, Addison, TX, has been assigned a patent (10,854,627) developed by Moriyama, Takumi, Shimizu, Satoshi, and Sakakibara, Kiyohiko, Yokkaichi, Japan, for a “three-dimensional memory device containing a capped insulating source line core and method of making the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”In-process source-level material layers including a source-level sacrificial layer are formed over a substrate, and an alternating stack of insulating layers and spacer material layers and memory stack structures are formed over the in-process source-level layers. A backside trench is formed through the alternating stack, and a source cavity is formed by removing the source-level sacrificial layer employing an etchant provided through the backside trench. A source contact layer including a doped semiconductor material is formed on vertical semiconductor channels of the memory stack structures within the source cavity. The source contact layer includes an unfilled cavity, which is subsequently filled with a silicon nitride liner, a silicon oxide fill material and a semiconductor cap. A semiconductor oxide structure can be formed by filling voids in the silicon oxide fill material by oxidizing the semiconductor cap into a thermal semiconductor oxide material portion.”

The patent application was filed on June 29, 2018 (16/023,035).

Three-dimensional memory
SanDisk Technologies LLC, a Western Digital Corp. company, Addison, TX, has been assigned a patent (10,854,619) developed by Chibvongodze, Hardwell, Nishikawa, Masatoshi, Nagoya, Japan, Ookuma, Naoki, Yokohama, Japan, Ariki, Takuya, and Miwa, Toru, Yokohama, Japan, for a “three-dimensional memory device containing bit line switches.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.”

The patent application was filed on December 7, 2018 (16/213,180).

Randomly writable memory
SanDisk Technologies LLC, a Western Digital Corp. company, Addison, TX, has been assigned a patent (10,853,244) developed by Petti, Christopher, Mountain View, CA, and Ranganathan, Srikanth, San Jose, CA, for “randomly writable memory device and method of operating thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A method of writing data to a DNA strand comprises cutting an address block of a selected address-data block unit of the DNA strand to form first and second DNA strings, and inserting a replacement address-data block that includes a replacement data segment between the first DNA string and the second DNA string to provide a rewritten DNA strand having valid address followed by valid data and an invalid address followed by invalid data.”

The patent application was filed on May 25, 2017 (15/604,994).

Non-volatile memory with capacitors using metal under signal line or above device capacitor
SanDisk Technologies LLC, a Western Digital Corp. company, Addison, TX, has been assigned a patent (10,847,452) developed by Lin, Luisa, Redwood City, CA, Dunga, Mohan, Santa Clara, CA, Ramachandra, Venkatesh P., San Jose, CA, Rabkin, Peter, and Higashitani, Masaaki, Cupertino, CA, for a “non-volatile memory with capacitors using metal under signal line or above a device capacitor.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A non-volatile storage apparatus comprises a non-volatile memory structure and a plurality of I/O pads in communication with the non-volatile memory structure. The I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads. The non-volatile storage apparatus further comprises one or more capacitors connected to the power I/O pad and the ground I/O pad. The one or more capacitors are positioned in one or more metal interconnect layers below the signal lines and/or above device capacitors on the top surface of the substrate.”

The patent application was filed on October 23, 2018 (16/168,232).

Non-volatile memory with countermeasure for over programming
SanDisk Technologies LLC, a Western Digital Corp. company, Addison, TX, has been assigned a patent (10,839,928) developed by Yang, Xiang, Santa Clara, CA, and Hemink, Gerrit Jan, San Ramon, CA, for a “non-volatile memory with countermeasure for over programming.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A non-volatile storage system includes a mechanism to compensate for over programming during the programming process. That is, after the programming process starts for a set of data and target memory cells, and prior to the programming process completing for the set of data and the target memory cells, the system determines whether a first group of the memory cells has more than a threshold number of over programmed memory cells. If so, then the system adjusts programming of a second group of memory cells to reduce the number of programming errors.”

The patent application was filed on May 16, 2019 (16/413,882).

Predictive boosting for 3D NAND
SanDisk Technologies LLC, a Western Digital Corp. company, Addison, TX, has been assigned a patent (10,839,923) developed by Yang, Xiang, San Jose, CA, for “predictive boosting for 3D NAND.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Non-volatile, high performance memory devices balance speed and reliability, which can include channel boosting to reduce data error rates in the memory cells. Vertical NAND strings exhibit greater program disturb (errors) the higher the wordline is on the string. The present disclosure applies a boosted bit line voltage or an increased precharge time when the programming reaches a level (wordline number) where it has been determined that errors due to program disturb may be an issue. The boost to the bit line may occur after a stored wordline value or based on a calculated number of errors at a previous wordline. In an example, the bit line stays the same as the prior world line programming operation until the likely program disturb is determined.”

The patent application was filed on June 7, 2019 (16/434,436).