R&D: Comprehensive Study of Double-Density Hemi-Cylindrical 3D NAND Flash

IEEE Transactions on Electron Devices has published an article written by Tzu-Hsuan Hsu, Hang-Ting Lue, Pei-Ying Du, Wei-Chen Chen, Teng-Hao Yeh, Lou Lee, Chia-Jung Chiu, Keh-Chung Wang, Chih-Yuan Lu, Department of Nano Technology Research and Development, Macronix International Company, Ltd., Hsinchu 300, Taiwan, R.O.C.

Abstract: “A novel double-density hemi-cylindrical (HC) structure 3-D NAND Flash architecture was demonstrated (Lue et al., 2019). HC 3-D NAND squeezes the gate-all-around (GAA) hole in one direction, followed by a slit cut to split the GAA device to produce twin cells, thus creating >2.5 times of memory density than standard GAA 3-D NAND at the same stacking layer. It is demonstrated that the extremely scaled HC 3-D NAND shows excellent 100k endurance and large memory window >10 V. Contrary to the standard GAA 3-D NAND, HC device has special edge effect issue. For taller HC device, a “wake-up” effect (Du et al., 2020) by an initial strong -FN erasing can introduce gate injected electrons that electrically suppress the parasitic edge and in turn “wake-up” the device to produce a larger programming window. TCAD simulation clearly shows asymmetrical E-field distribution from bottom oxide field to top oxide field at Region I (HC tip) and Region II (bottom edge). Through the comprehensive investigation of HC device “wake-up” effect and strong -FN for initial reset, the variation of cell to cell operation window is minimized and aligned to extremely scaled “hero” HC devices that enjoy field enhancement effect (Hsu et al., 2007). Our results suggest a promising path of 3-D NAND device toward aggressive dimension scaling and large memory window.“