RISC-V Summit: Seagate Designed 2 Processors Based on Open RISC-V Instruction Set Architecture

Seagate Technology plc designed 2 processors based on the open RISC-V instruction set architecture (ISA).

One of the open standards-enabled cores is designed for performance and the other is area-optimized. The performance processor has already been built with RISC-V-enabled silicon and demonstrated as functional in HDDs. The area-optimized core has been designed and is in the process of being built.

Because both processors offer RISC-V security features, the benefits add up to more robust edge-to-cloud data trustworthiness, security, and mobility-all essential in the era when so much data is on the move.

This announcement, made at the Virtual RISC-V Summit 2020, is the first public report on the results of the firm‘s several years of collaboration with RISC-V International.

“Having shipped close to one billion cores over the last year, Seagate has developed significant expertise in system-on-a-chip design,” said Cecil Macgregor, VP, ASIC development. “We now expanded the capability to add customized RISC-V cores to our portfolio, which is critical to future products. We live in a time of unprecedented growth of enterprise data-and much of this data is in motion. These cores will allow devices to share a common RISC-V ISA. Using open security architectures, they will enable more secure movement of data.“

The performance core offers up to triple the performance for real-time, critical HDD workloads vs. current solutions. In an initial use case, this core enabled the company  to increase the real-time processing power available. The processor paves the way for finer positioning by implementation of advanced servo (motion control) algorithms.

The area-optimized core boasts a highly configurable micro-architecture and feature set. It’s optimized both for footprint and power savings. It powers auxiliary, supporting, or background workloads. It can execute security-sensitive edge computational operations (including next-gen post-quantum cryptography) while targeting a small-footprint implementation of security features over performance.

One of the key use cases for this core is security. A member of OpenTitan, the company is committed to open and transparent security.

“We see a significant potential for open, extensible architectures like RISC-V,” said Dominic Rizzo, project director, OpenTitan, and engineering lead, Google Cloud. “OpenTitan’s open-source implementation benefits from RISC-V’s open nature, enabling pan-industry transparency, trust,, and silicon security. Because Seagate understands the promise of RISC-V for security, we are excited to collaborate with Seagate on the open-sorce silicon root of trust we are currently developing.“

The Seagate cores will also accelerate real-time analysis in the data center and at the edge. Such analysis is crucial to the work of scientific communities with mass data needs.

“At Los Alamos National Laboratory, using computational storage to move processing near data has begun to alter the way we analyze data and perform scientific discovery,” said Brad Settlemyer, senior research scientist, Los Alamos National Laboratory. “By having compute integrated closely with storage we are able to create persistent data transformations that speed up data analysis by 1000-fold. This greatly relieves our primary compute tier from these tasks. We will be continuing our drive toward efficiency gains for our mission needs by partnering with vendors and actively participating in important industry initiatives like computational storage.“

The company has determined that solutions on this front tend to involve custom silicon: that’s where RISC-V shines.

“Introducing RISC-V to storage devices creates an opportunity to implement application-specific computational capabilities that enable massive parallel computational storage solutions,” said John Morris, CTO, Seagate. “We believe that these architectures support many important use cases that include scientific simulation (for example, weather prediction) as well as the learning part of ML.“

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