As the HPC demands of data center workloads increase, new low-latency signal transmission technology is required to advance the performance in AI, ML , Advanced Driver Assisted Systems (ADAS) and other computational workload applications.
XpressConnect retimers triple the reach of PCIe Gen 5 electrical signals, which enables data center equipment providers to harness the advancement in compute IO performance while providing the required flexibility and connectivity for advanced hardware architectures. These retimers deliver low-latency signal transmission that enables the demanding computational workloads in AI, ML, communication systems and HPC applications.
“With increasing storage, compute and memory bandwidth demands, hyperscale data center, server and storage providers have continued to look to Microchip for leading compute, storage and memory connectivity solutions,” said Andrew Dieckmann, associate VP, marketing and applications engineering, data center solutions business unit. “Microchip is uniquely positioned to deliver seamless interoperability with XpressConnect retimers given our extensive portfolio of PCIe Switchtec and Flashtec products and our close relationships with industry partners, providing lower engineering costs and faster time to market for our customers.“
The XpressConnect family delivers extended reach at >80% lower latency than the PCIe spec, with a pin-to-pin latency of <10 nanoseconds.
These retimers are available in multiple lane count variants of up to 16 lanes of PCIe Gen 5 to connect to a range of PCIe and CXL devices. They support passive copper and optical cables and include high-reliability features such as hot-plug and surprise-plug. XpressConnect delivers a cost-effective solution for motherboard, backplane, cable and riser card use cases by enabling system integrators to use lower-cost cables and board materials.
To enable rapid time to market for customers, the company has partnered with Intel Corp. to develop an XpressConnect reference design in a standard riser card form-factor that will be available to customers on Intel’s Resource and Design Center. XpressConnect also supports ChipLink diagnostic and development tooling to reduce engineering development cost and accelerate time to market.
“PCIe 5.0 and CXL will enhance the workload performance and capabilities of Intel’s future Xeon Scalable processor code-named ‘Sapphire Rapids.’ As with all new standards, adoption of PCIe 5.0 and CXL will be dependent on validation and interoperability delivered by industry leaders,” said Jim Pappas, director, technology initiatives, Intel Corp. “Microchip and Intel have a long history of collaboration on PCIe solutions, and we are excited to continue our joint efforts to deliver a robust ecosystem that enables easy adoption of next-gen PCIe 5.0 and CXL 1.1/2.0 solutions with low-latency retimers.“
“Microchip is a key contributor to the CXL Consortium, both as a CXL board member and participant in the technical working groups developing the CXL spec,” said Barry McAuliffe, president, CXL Consortium. “Microchip’s XpressConnect low-latency retimers are a welcome addition to the CXL ecosystem.“
The company has released a set of design-in collateral, reference designs, evaluation boards and tools to support customers building systems that take advantage of the high-bandwidth of PCIe Express 5.0 and low-latency connectivity of CXL 1.1/2.0. The firm’s ChipLink diagnostic GUI used across all of Microchip’s data center products has been extended to support XpressConnect retimers to provide extensive debug, diagnostics, configuration and forensics tools.
XpressConnect retimers are sampling to qualified customers.
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