NandEXT Assigned Patent

NandEXT S.R.L., Localita Dogana, San Marino, has been assigned a patent (10,790,854) developed by Viterbo, Emanuele, and Wijekoon, Viduranga, Melbourne, Australia, for a “coset probability based majority-logic decoding for non-binary LDPC codes.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A method for iteratively decoding read bits in a solid state storage device. The read bits are encoded with a Q-ary LDPC code defined over a binary-extension Galois field GF (2.sup.r) and having length N. The method comprises determining a binary Tanner graph of the Q-ary LDPC code based on a Q-ary Tanner graph of the Q-ary LDPC code, and based on a binary coset representation of the Galois field GF (2.sup.r). The binary Tanner graph comprises, for each Q-ary variable node/Q-ary check node pair of the Q-ary Tanner graph, (2.sup.r-1) binary variable nodes each one being associated with a respective one of said cosets, (2.sup.r-1-r) binary parity-check nodes each one being connected to one or more of said, 2.sup.r-1) binary variable nodes according to said binary coset representation of the Galois field GF (2.sup.r) wherein each binary parity-check node corresponds to a respective parity-check equation associated with a first parity-check matrix that results from said binary coset representation, and (2.sup.r-1) binary check nodes each one being connected to a respective one of said (2.sup.r-1) binary variable nodes according to a second parity-check matrix defining the Q-ary LDPC code. The method further comprises, based on a Majority-Logic decoding algorithm, mapping the read bits into N symbols each one including, for each bit thereof, a bit value and a reliability thereof, and providing each symbol of said N symbols to a respective Q-ary variable node, wherein each bit of said each symbol is provided to a respective one of the (2.sup.r-1) binary variable nodes of said respective Q-ary variable node. The method also comprises, based on the Majority-Logic decoding algorithm, iteratively performing the following steps: (i) at each binary check node, determining a first bit estimate and a first bit reliability of each bit of the respective symbol according to, respectively, a second bit estimate and a second bit reliability of that bit that are determined at each binary variable node connected to that binary check node (and ii) at each binary variable node, updating the second bit estimate and the second bit reliability of each bit of the respective symbol based on the first bit estimate and the first bit reliability of that bit determined at each binary check node connected to that binary variable node, and based on the parity-check equation associated with the first parity-check matrix and corresponding to the parity-check node connected to that binary variable node.”

The patent application was filed on January 17, 2019 (16/250,921).