Cadence Design Systems Assigned Patent

Cadence Design Systems, Inc., San Jose, CA, has been assigned a patent (10,769,013) developed by MacLaren, John M., Laws, Landon, Olson, Carl Nels, Austin, TX, and Shepherd, Thomas J., Cedar Park, TX, for a “caching error checking data for memory having inline storage configurations.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Various embodiments provide for caching of error checking data for memory having inline storage configurations for primary data and error checking data for the primary data. In particular, various embodiments described herein provide for error checking data caching and cancellation of error checking data read commands for memory having inline storage configurations for primary data and associated error checking data. Additionally, various embodiments described herein provide for combining/canceling of error checking data write commands for memory having inline storage configurations for primary data and associated error checking data.”

The patent application was filed on June 11, 2018 (16/005,427).