Intel Assigned Thirteen Patents

3D NAND structures including group III-N material channels
Intel Corporation, Santa Clara, CA , has been assigned a patent (10,727,241) developed by Dasgupta, Sansaptak, Hillsborough, OR, Majhi, Prashant, San Jose, CA, Then, Han Wui, and Radosavljevic, Marko, Portland, OR, for “3D NAND structures including group III-N material channels.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Techniques are disclosed for forming three-dimensional (3D) NAND structures including group III-nitride (III-N) material channels. Typically, polycrystalline silicon, poly-Si) channels are used for 3D NAND structures, such as 3D NAND flash memory devices. However, using III-N channel material for 3D NAND structures offers numerous benefits over poly-Si channel material, such as relatively lower resistance in the channel, relatively higher current densities, and relatively lower leakage. Therefore, using III-N channel material enables an increased number of floating gates or storage cells to be stacked in 3D NAND structures, thereby leading to increased capacity for a given integrated circuit footprint, (e.g., increased GB/cm.sup.2). For instance, use of III-N channel material can enable greater than 100 floating gates for a 3D NAND structure. Other embodiments may be described and/or disclosed.”

The patent application was filed on June 30, 2016 (16/303,485).

Redirecting memory access commands sent to unusable memory partitions
Intel Corporation, Santa Clara, CA , has been assigned a patent (10,725,933) developed by Pico, Lady Nataly Pinilla, El Dorado Hills, CA, for “method and apparatus for redirecting memory access commands sent to unusable memory partitions.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”In one embodiment, an apparatus comprises a plurality of memory partitions, each memory partition comprising an array of 3D crosspoint memory, and a storage device controller comprising a memory comprising memory cells to store addresses of replacement memory partitions and addresses of unusable memory partitions and a partition address translation engine coupled to the memory, the partition address translation engine comprising logic to determine whether to redirect a memory access command received from a host computing device to a replacement memory partition based on the contents of the memory.”

The patent application was filed on December 30, 2016 (15/394,933).

Graphics memory extended with nonvolatile memory
Intel Corporation, Santa Clara, CA , has been assigned a patent (10,725,929) developed by Zhu, Jianfang, Ferreira, Cristiano J., Qiu, Bo, Lakshman, Ajit Krisshna Nandyal, Talpallikar, Nikhil, Shivakumar, Deepak Gandiga, Hillsboro, OR, Guttridge, Brandt M., Folsom, CA, Pallister, Kim, Portland, OR, Soqui, Frank J., Hillsboro, OR, Srivatsa, Anand, Portland, OR, Schluessler, Travis T., Hillsboro, OR, Appu, Abhishek R., El Dorado Hills, CA, Shah, Ankur N., Ray, Joydeep, Folsom, CA, Koker, Altug, El Dorado Hills, CA, and Kennedy, Jonathan, Bristol, Great Britain, for a “graphics memory extended with nonvolatile memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”An embodiment of an electronic processing system may include an application processor, system memory communicatively coupled to the application processor, a graphics processor communicatively coupled to the application processor, graphics memory communicatively coupled to the graphics processor, and persistent storage media communicatively coupled to the application processor and the graphics processor to store one or more graphics assets, wherein the graphics processor is to access the one or more graphics asset mapped from the persistent storage media. The persistent storage media may include a low latency, high capacity, and byte-addressable nonvolatile memory. The one or more graphics assets may include one or more of a mega-texture and terrain data. Other embodiments are disclosed and claimed.”

The patent application was filed on April 10, 2017 (15/483,741).

Data storage connectors with parallel array of dense memory cards and high airflow
Intel Corporation, Santa Clara, CA , has been assigned a patent (10,721,832) developed by Nelson, Michael D., Mountain View, CA, Khan, Jawad B., Portland, OR, and Webb, Randall K., Hillsboro, OR, for a “data storage system connectors with parallel array of dense memory cards and high airflow.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Data storage system connectors are described for a parallel array of dense memory cards that allow high airflow. In one example, a connector has a horizontal plane board having a plurality of memory connectors aligned in a row and a plurality of external interfaces, a plurality of memory cards, each having an edge connector at one end of the memory card to connect to a respective memory connector of the board, each memory card extending horizontally parallel to each other memory card and extending vertically and orthogonally from the board, and a plurality of interface connectors each to connect an edge connector to a respective board connector, the interface connectors extending horizontally from the one end of the memory cards and vertically to the respective plane board connector.”

The patent application was filed on March 14, 2016 (16/083,411).

Data compression in wearable device
Intel Corporation, Santa Clara, CA , has been assigned a patent (10,720,942) developed by Natarajan, Venkat, Bangalore, India, Pendekanti, Nikita, Hyderabad, India, and Ranganathan, Kumar, Bangalore, India, for “apparatus and method for data compression in a wearable device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Described is an apparatus and method for data compression using compressive sensing in a wearable device. Described is also a machine-readable storage media having instruction stored thereon, that when executed, cause one or more processors to perform an operation comprising: receive an input signal from a sensor, convert the input signal to a digital stream, and symmetrically pad on either ends of the digital stream with a portion of the digital stream to form a padded digital stream.”

The patent application was filed on June 1, 2016 (15/741,497).

Technologies for computational storage via offload kernel extensions
Intel Corporation, Santa Clara, CA , has been assigned a patent (10,719,462) developed by Trika, Sanjeev, Portland, OR, for “technologies for computational storage via offload kernel extensions.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Technologies for data processing or computation on data storage devices include a data storage controller. The data storage controller is configured to receive a data request from a compute device, determine an input data range specified by the compute device to be processed in the data storage device without sending data located at the input data to the compute device, read input data from the input data range, perform a data operation on the input data specified by the compute device to generate output data, and write the output data to an output data range specified by the compute device.”

The patent application was filed on September 25, 2018 (16/141,411).

Implementing multi-level memory hierarchy
Intel Corporation, Santa Clara, CA , has been assigned a patent (10,719,443) developed by Ramanujan, Raj K., Federal Way, WA, Agarwal, Rajat, Cheng, Kai, Portland, OR, Polepeddi, Taarinya, Saratoga, CA, Raad, Camille C., Folsom, CA, Zimmerman, David J., El Dorado Hills, CA, Swaminathan, Muthukumar P., Folsom, CA, Ziakas, Dimitrios, Hillsboro, OR, Kumar, Mohan J., Aloha, OR, Coury, Bassam N., Dupont, WA, and Hinton, Glenn J., Portland, OR, for “apparatus and method for implementing a multi-level memory hierarchy.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as ‘far memory.’ Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as ‘near memory.’.”

The patent application was filed on March 25, 2019 (16/363,992).

Management and access of distributed data sources
Intel Corporation, Santa Clara, CA , has been assigned a patent (10,706,162) developed by Dave, Manish, Folsom, CA, Hassan, Vishwa, Chandler, AZ, Gowda, Bhaskar D., Hillsboro, OR, and Shekhar, Mrigank, Camas, WA, for “device and methods for management and access of distributed data sources.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A device and method for provided access to distributed data sources includes a cloud security server configured to associate any number of data sources and client devices with a cloud security server account. The cloud security server assigns trust levels to the data sources and the client devices. A client device requests data from the cloud security server. The cloud security server authenticates the client device and verifies the trust levels of the client device and the requested data. If verified, the cloud security server brokers a connection between the client device and the data source, and the client device accesses the requested data. Data sources may include cloud service providers and local storage devices. The cloud security server may assign a trust level to a client device for a limited time or revoke a trust level assigned to a client device. Other embodiments are described and claimed.”

The patent application was filed on November 29, 2016 (15/363,157).

Dynamic reliability levels for storage devices
Intel Corporation, Santa Clara, CA , has been assigned a patent (10,700,703) developed by Khan, Jawad B., Trika, Sanjeev N., Tickoo, Omesh, and Wu, Wei, Portland, OR, for a “dynamic reliability levels for storage devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”To address the storage needs of applications that work with noisy data, (e.g. image, sound, video data), where errors can be tolerated to a certain extent and performance is more critical than data fidelity, dynamic reliability levels enable storage devices capable of storing and retrieving data with varying degrees of data fidelity to dynamically change the degree of data fidelity in response to an application’s request specifying reliability level. By allowing the application to specify the reliability level at which its data is stored and retrieved, dynamic reliability levels can increase read/write performance without sacrificing application accuracy. The application can specify reliability levels for different types or units of data, such as different reliability levels for metadata as opposed to data and so forth.”

The patent application was filed on June 28, 2018 (16/022,631).

Techniques to recover data in network storage
Intel Corporation, Santa Clara, CA , has been assigned a patent (10,698,765) developed by Jin, Jun, Shanghai, China, for “techniques to recover data in a network storage system.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Examples include techniques to recover data in a storage. In some examples, an erasure code may be implemented to protect a data file or data object stored to nodes of a networked storage system. Corrupted data included in source data blocks may be recovered and verified based on the erasure code.”

The patent application was filed on December 23, 2015 (15/778,616).

Mechanisms for SAS-free cabling in rack scale design
Intel Corporation, Santa Clara, CA , has been assigned a patent (10,687,434) developed by Kumar, Mohan J., Aloha, OR, and Nachimuthu, Murugasamy K., Beaverton, OR, for “mechanisms for SAS-free cabling in rack scale design.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Mechanisms for SAS-free cabling in Rack Scale Design (RSD) environments and associated methods, apparatus, and systems. Pooled compute drawers containing multiple compute nodes are coupled to pooled storage drawers using fabric infrastructure, such as Ethernet links and switches. The pooled storage drawers includes a storage distributor that is coupled to a plurality of storage devices and includes one or more fabric ports and a PCIe switch with multiple PCIe ports. Under one configuration, the PCIe ports are connected to one or more IO hubs including a PCIe switch coupled to multiple storage device interfaces that are coupled to the storage devices. In another configuration, the PCIe ports are connected directly to PCIe storage devices. The storage distributor implements a NVMe-oF server driver that interacts with an NVMe-oF client driver running on compute nodes or a fabric switch. The drivers logically couple the storage devices over the fabric infrastructure to the compute nodes in a manner that appears the storage devices are local devices.”

The patent application was filed on December 30, 2016 (15/395,855).

Application based checkpointing control for storage
Intel Corporation, Santa Clara, CA , has been assigned a patent (10,685,097) developed by Sukhomlinov, Vadim, Santa Clara, CA, and Trika, Sanjeev N., Portland, OR, for an “application based checkpointing control for storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”An embodiment of a semiconductor apparatus may include technology to receive an application-related checkpoint request corresponding to a file of a file system stored on a persistent storage media, and determine one or more checkpoint operations internal to the persistent storage media to perform the application-related checkpoint request. Other embodiments are disclosed and claimed.”

The patent application was filed on December 29, 2017 (15/858,768).

Techniques for detecting and correcting errors in data
Intel Corporation, Santa Clara, CA , has been assigned a patent (10,678,636) developed by Durham, David M., Beaverton, OR, and Trika, Sanjeev N., Portland, OR, for “techniques for detecting and correcting errors in data.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Various embodiments are generally directed to techniques for managing errors in data, such as with error-correcting code (ECC), for instance. Some embodiments are particularly directed to providing one or more of error detection, location, and correction for a set of storage memory devices with a management memory device. In one or more embodiments, each of the storage and management memory devices may include a memory chip, such as one of a set of memory chips included in a dual in-line memory module (DIMM). For instance, each memory device be a dynamic random-access memory (DRAM) integrated circuit included in a DIMM. In various embodiments, the set of storage management memory devices may be used to store a memory line, such as an evicted cache line. In many embodiments, cryptographically secure memory encryption and/or integrity may also be provided for the set of storage memory devices with the management memory device.”

The patent application was filed on February 28, 2018 (15/908,205).