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R&D: Multi-Bit Read and Write Methodologies for Diode-MTJ Crossbar Array

Results indicate biasing half-selected cells by 700mV can enable reading as much as 512bits while sustaining 512×512 crossbar with 2.04 years retention.

IEEE Xplore has published, in 2020 21st International Symposium on Quality Electronic Design (ISQED) proceedings, an article written by Mohammad Nasim Imtiaz Khan, and Swaroop Ghosh, School of EECS, The Pennsylvania State University, University Park,PA, USA.

Abstract: Crossbar arrays using emerging Non-Volatile Memory (NVM) technologies offer high density, fast access speed and low-power. However, the bandwidth of the crossbar is limited to single-bit read/write per access to avoid the selection of undesirable bits. In this work, we propose a technique to perform multi-bit read and write in a diode-MTJ (Magnetic Tunnel Junction) crossbar array. The simulation shows that the biasing voltage of half-selected cells can be adjusted to improve the sense margin during read which in turn, reduces the sneak path through the half-selected cells. Results indicate biasing the half-selected cells by 700mV can enable reading as much as 512bits while sustaining 512×512 crossbar with 2.04 years retention. During write operation, the half-selected cells are biased with a pulse voltage source in addition to V/2 scheme which increases the write latency of these cells and enables writing 2bits while keeping the half-selected bits undisturbed. The 2bit writing requires pulsing by 50mV to optimize energy.

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