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R&D: Applying Multiple Level Cell to Non-Volatile FPGAs

Compared to SRAM-based FPGAs, proposed architecture with proposed CAD flow can reduce area, critical path delay and leakage power by 31%, 10%, and 95%, respectively.

ACM Transactions on Embedded Computing Systems has published an article written by Ke Liu, Mengying Zhao, Lei Ju, School of Computer Science and Technology, Shandong University, China, Zhiping Jia, School of Computer Science and Technology, Shandong ...

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