R&D: Applying Multiple Level Cell to Non-Volatile FPGAs

ACM Transactions on Embedded Computing Systems has published an article written by Ke Liu, Mengying Zhao, Lei Ju, School of Computer Science and Technology, Shandong University, China, Zhiping Jia, School of Computer Science and Technology, Shandong University, China, Jingtong Hu, Department of Electrical and Computer Engineering, University of Pittsburgh, USA, and Chunjason Xue, Department of Computer Science, City University of Hong Kong, Hong Kong, China.

Abstract: “Static random access memory– (SRAM) based field programmable gate arrays (FPGAs) are currently facing challenges of limited capacity and high leakage power. To solve this problem, non-volatile memory (NVM) is proposed as the alternative to build non-volatile FPGAs (NVFPGAs). Even though the feasibility of NVFPGA has been confirmed, the utilization of multiple level cells (MLCs) has not been fully exploited yet. In this article, we study architecture of MLC-based NVFPGAs, and propose five cluster structures. To give detailed comparisons and extensive discussions, we conduct experiments for area, performance and leakage power evaluation. Based on explorations of the characteristics of MLC-based NVFPGAs, we further present MLC-aware timing-driven packing method to improve delay. In critical paths, our proposed method reduces the overhead of the additional delay in slow MLC cells. Experiments show that, compared to SRAM-based FPGAs, the proposed architecture with the proposed CAD flow can reduce the area, critical path delay and leakage power by 31%, 10%, and 95%, respectively.“