R&D: Reliability and Breakdown Study of Erase Gate Oxide in Split-Gate Non-Volatile Memory Device

IEEE Xplore has published, in 2020 IEEE International Reliability Physics Symposium (IRPS) proceedings, an article written by L. Luo, K. Shubhakar, S. Mei, N. Raghavan, Singapore University of Technology and Design, Engineering Product Development, Singapore, 487 372,  F. Zhang, D. Shum, Globalfoundries Singapore Pte. Ltd., Singapore, 738406, and K. L. Pey, Singapore University of Technology and Design, Engineering Product Development, Singapore, 487 372.

Abstract: “The electrical reliability study of 40 nm embedded non-volatile memory (NVM) technology was widely studied with respect to data retention and cycling. However, intrinsic reliability of NVM gate oxide was rarely reported. Here, we present key results on soft breakdown (SBD) and hard breakdown (HBD) events in split-gate NVM (SG-NVM) together with most likely breakdown (BD) location in erase gate (EG) oxide. A new method of nanoprobe electrical stressing was applied on EG oxide and physical failures were successfully observed using transmission electron microscopy (TEM). Combined kinetic Monte Carlo (KMC) and finite element method (FEM) simulation results show that the BD occurs in EG oxide associated with high-electric field during erase operation. The HBD path can be clearly identified and shows melting of whole W plug and copper, connected to erase Poly-Si gate on top of EG oxide. Thus, our results provide critical information to identify the reliability weak link of the SG-NVM device and, electrical and physical behavior of the EG oxide during the SBD and HBD events.“