R&D: Exploiting Dynamic Error Prechecking Scheme to Improve Read Performance of SSD

IEEE Xplore has published, in 2020 IEEE International Memory Workshop (IMW) proceedings, an article written by Weihua Liu, Fei Wu, Meng Zhang, Wuhan National Laboratory for Optoelectronics, Key Laboratory of Information Storage System, and Engineering Research Center of data storage systems and Technology, Ministry of Education of China, Huazhong University of Science and Technology, Wuhan 430074, China, and the Shenzhen Research Institute, Huazhong University of Science and Technology, Shenzhen 518000, China, Chengmo Yang, Dept. of Electrical & Computer Engineering, University of Delaware, Newark, United States of America, Zhonghai Lu, School of Electrical Engineering and Computer Science, KTH Royal Institute of Technology, Stockholm, Sweden, Jiguang Wan, and Changsheng Xie, Wuhan National Laboratory for Optoelectronics, Key Laboratory of Information Storage System, and Engineering Research Center of data storage systems and Technology, Ministry of Education of China, Huazhong University of Science and Technology, Wuhan 430074, China, and the Shenzhen Research Institute, Huazhong University of Science and Technology, Shenzhen 518000, China.

Abstract: “3D NAND flash memory is gradually being widely used in solid state drives (SSD), leading to increasing storage capacity. However, the read performance of SSD is sacrificed for decoding operations which are executed to guarantee the data reliability. No matter whether the data have bit errors, they will be sent to error correcting code (ECC) engine to decode, introducing a high read delay of SSD. Error prechecking can help to avoid the redundant decoding operations for the error-free data, but it induces extra checking overhead to the error data. Motivated by this, we carry out comprehensive experiments to analyze the distribution of bit errors in 3D NAND flash memory. The preliminary experimental results show that there are a large number of pages read without errors in the early lifetime of 3D NAND flash memory. Based on the observations and analyses, we propose a model to estimate the error-free ratio, and utilize it to design a dynamic error prechecking scheme (DEPS) to bypass the decoding operation for the error-free data in 3D NAND flash memory and improve the read performance of SSD. Furthermore, by dividing a large page into small subpages, DEPS releases more error-free data, which significantly improves the read performance of SSD. Evaluation results from real-world traces demonstrate that by implementing DEPS, the average read performance of SSD is enhanced by 35% 55% with 3D MLC NAND flash memory.“