R&D: Extremely Biased Error Correction Method to Reduce Read Disturb Errors of 3D-TLC NAND Flash Memories by 60%

IEEE Xplore has published, in 2020 IEEE International Memory Workshop (IMW) proceedings, an article written by Hiroki Aihara, Kyosuke Maeda, Shun Suzuki, and Ken Takeuchi, Chuo University, Department of Electrical, Electronic, and Communication Engineering, Tokyo, Japan.

Abstract: “This paper proposes Extremely Biased Error Correction (EBEC) to reduce extremely biased errors occurred in various memory devices. Extremely biased errors are errors which the bit-error rate (BER) of one state is extremely high. Proposed EBEC detects and corrects the errors and secures the reliability of NAND flash by using flag cells. In this paper, proposed EBEC is applied to Charge-Trap (CT) 3D-triple-level cell (TLC) NAND flash, which has many ‘Erase’-state errors in read-hot data. As a result, proposed EBEC reduces BER of ‘Erase’-state by 99.3% at 300K read cycles. In addition, compared with Random data, overall BER is reduced by 60.0% in proposed EBEC, which corrects extremely biased error more than BCH ECC. Various devices have extremely biased error. Therefore, Proposed EBEC is applied to not only NAND flash but also other memory devices.“