CalTech Assigned Patent
Error characterization and mitigation for 16nm MLC NAND flash memory under total ionizing dose effect
By Francis Pelletier | June 10, 2020 at 2:19 pmCalifornia Institute of Technology, Pasadena, CA , has been assigned a patent (10,665,310) developed by Li, Yue, Pasadena, CA, and Bruck, Jehoshua, La Canada Flintridge, CA, for “error characterization and mitigation for 16nm MLC NAND flash memory under total ionizing dose effect.“
The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A radiation hardened NAND flash memory data storage device suitable for space flight having a plurality of memory cells configured to store data values in accordance with a predetermined rank modulation scheme and a memory controller that receives a current error count from an error decoder of the data device for one or more data operations of the flash memory device and selects an operating mode for data scrubbing in accordance with the received error count and a program cycles count. Methods of operating the data storage device are also described.”
The patent application was filed on January 28, 2019 (16/259,143).
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