ScaleFlux Assigned Three Patents

Ensuring in-storage data atomicity and consistency at low cost
ScaleFlux, Inc., San Jose, CA, has been assigned a patent (10,628,066) developed by Wu, Qi, Li, Qing, and Li, Jiangpeng, San Jose, CA, for “ensuring in-storage data atomicity and consistency at low cost.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A storage infrastructure and method for efficiently handing block I/O requests. An infrastructure is described that includes flash memory and a controller that includes: a two dimensional (2D) linked list structure for temporarily storing BIO requests, wherein each BIO request specifies a set of LBAs and wherein the 2D linked list structure includes N vertical linked lists, a BIO request loader that applies a hash function to each LBA in a received BIO request to associate each LBA to one of N hash values, and loads the received BIO request into a horizontal linked list in the 2D linked list structure in which each LBA resides within a vertical linked list based on an associated hash values, and a linked list manager that determines which LBAs in the 2D linked list structure are eligible for processing and when a horizontal linked list can be removed.”

The patent application was filed on May 21, 2018 (15/984,538).

Enhancing flash translation layer to improve performance of databases and filesystems
ScaleFlux, Inc., San Jose, CA, has been assigned a patent (10,620,846) developed by Zhang, Tong, Albany, NY, Liu, Yang, Milpitas, CA, Sun, Fei, Irvine, CA, and Zhong, Hao, Los Gatos, CA, for “enhancing flash translation layer to improve performance of databases and filesystems.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”An enhanced FTL system and method are provided for eliminating redundant write operations. A method is disclosed, including: processing a data write operation from a host that deploys a journaling scheme, wherein the data write operation includes a specified LBA that maps to a PBA in a SSD memory, calculating a signature of a data block during a write operation, detecting whether the data write should be handled as journal or non-journal write operation without assistance from the host, in response to a detected journal write operation, allocating a new PBA, writing the data block to the new PBA, updating a mapping table with a new LBA-PBA mapping, and inserting the signature into a signature table for the new LBA-PBA mapping, and in response to a detected non-journal write operation, mapping the specified LBA to an existing PBA if the signature matches a stored signature in the mapping table.”

The patent application was filed on October 6, 2017 (15/726,839).

Storage infrastructure that employs low complexity encoder
ScaleFlux, Inc., San Jose, CA, has been assigned a patent (10,613,797) developed by Vernon, Mark, Park City, UT, Liu, Yang, Milpitas, CA, and Sun, Fei, Irvine, CA, for a “storage infrastructure that employs a low complexity encoder.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A storage infrastructure, method and encoder device for implementing low complexity encoding, The described encoder includes: a preprocessing system that assigns a code length to each unique symbol based on the frequency without performing a sort operation and determines maximum and minimum occurrence frequencies of symbols of each given code length, and the maximum and minimum code length among all the symbols, and a post processing system that cycles through each code length, determines if a maximum occurrence frequency of a current code length, associated with a first symbol, is greater than a minimum occurrence frequency of an adjacent code length, associated with a second symbol, and if greater, swaps code lengths of the first and second symbols.”

The patent application was filed on June 12, 2018 (16/006,170).