Solid State Storage Technology Assigned Four Patents

Solid state storage device and control method with prediction model to increase read speed
Solid State Storage Technology Corporation, Taipei, Taiwan, has been assigned a patent (10,629,289) developed by Zeng, Shih-Jia, Fu, Jen-Chien, Lu, Tsu-Han, and Chen, Kuan-Chun, Taipei, Taiwan, for “solid state storage device and control method with prediction model to increase read speed.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A solid state storage device is in communication with a host. The solid state storage device includes a control circuit and a non-volatile memory. The control circuit is in communication with the host. The control circuit includes an error correction circuit and a prediction model storage circuit. A prediction model is stored in the prediction model storage circuit. The non-volatile memory includes a memory cell array. The memory cell array includes plural blocks. Each of the blocks includes a corresponding state parameter. The control circuit determines a selected block from the memory cell array. The control circuit judges whether to perform a specified operation on the selected block according to the state parameter of the selected block and the prediction model.”

The patent application was filed on June 21, 2018 (16/014,200).

Solid state storage device and read table management
Solid State Storage Technology Corporation, Taipei, Taiwan, has been assigned a patent (10,629,269) developed by Zeng, Shih-Jia, Kuo, Chun-Wei, Chen, Kuan-Chun, and Fu, Jen-Chien, Taipei, Taiwan, for “solid state storage device and read table management method thereof .“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A read table management method for a solid state storage device includes the following steps. If the lowest computation value in a hot group is lower than the highest computation value in a cold group when a read table adjusting process is enabled, a first read voltage set corresponding to the lowest computation value in the hot group and a second read voltage set corresponding to the highest computation value in the cold group are swapped with each other. Consequently, the second read voltage set becomes to belong to the hot group, and the first read voltage set becomes to belong to the cold group.”

The patent application was filed on September 19, 2018 (16/135,159).

Flash memory testing according to error type pattern
Solid State Storage Technology Corporation, Taipei, Taiwan, has been assigned a patent (10,628,247) developed by Wu, Tsung-Hung, and Lin, Sin-Yu, Taipei, Taiwan, for a “flash memory testing according to error type pattern.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A storage method comprises storing a retry table, wherein the retry table recites a plurality of error type patterns, the error type patterns comprises a plurality of default error types, accessing data stored in the flash memory, wherein an access error caused when a control circuit reads the data, the control circuit reads the retry table and performs testing according to the error type patterns sequentially to determine a current error type of the access error, and the control circuit performs an adjusted accessing action according to the current error type.”

The patent application was filed on March 15, 2018 (15/921,738).

Solid state storage device and read retry
Solid State Storage Technology Corporation, Taipei, Taiwan, has been assigned a patent (10,606,518) developed by Zeng, Shih-Jia, Fu, Jen-Chien, Lu, Tsu-Han, and Yen, Hsiao-Chang, Taipei, Taiwan, for “solid state storage device and read retry method thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A solid state storage device includes a control circuit and a non-volatile memory. The control circuit includes a retry table. In addition, plural retry read-voltage sets are recorded in the retry table, and the retry table is divided into plural retry sub-tables. The plural retry read-voltage sets are classified into plural groups. The plural retry read-voltage sets are recorded into the corresponding retry sub-tables. The non-volatile memory is connected with the control circuit. During a read retry process of a read cycle, the control circuit performs a hard decoding process according to a retry sub-table of the plural retry sub-tables. If the hard decoding process fails, the control circuit performs a soft decoding process according to another retry sub-table of the plural retry sub-tables.”

The patent application was filed on October 19, 2018 (16/165,211).