Phison Assigned Ten Patents

Data merge method which reads first physical unit twice for respectively performing first stage programming operation and second stage programming operation on second physical unit
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (10,592,167) developed by Yeh, Chih-Kang, Kinmen County, Taiwan, for “data merge method which reads first physical unit twice for respectively performing first stage programming operation and second stage programming operation on second physical unit, memory storage device and memory control circuit unit.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”An exemplary embodiment of the disclosure provides a data merge method for a memory storage device. The method comprises: performing a data merge operation to store valid data collected from a source node comprising at least one first physical unit to a recycling node comprising a second physical unit. The data merge operation comprises: reading a first data from the at least one first physical unit by a first reading operation, performing a first stage programming operation on the second physical unit according to the first data, reading the first data from the at least one first physical unit again by a second reading operation after the first stage programming operation is performed, and performing a second stage programming operation on the second physical unit according to the first data read by the second reading operation.”

The patent application was filed on September 26, 2018 (16/141,990).

Data writing, memory control circuit unit and memory storage
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (10,586,596) developed by Lin, Wei, Taipei, Taiwan, Hsu, Yu-Cheng, Yilan County, Taiwan, and Chen, Szu-Wei, New Taipei, Taiwan, for “data writing method, memory control circuit unit and memory storage apparatus.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data writing method for a rewritable non-volatile memory module having a plurality of physical erasing units and a memory control circuit unit and a memory storage apparatus using the same are provided. Each of the physical erasing units has a plurality of physical programming unit sets, and each of the physical programming unit sets has a plurality of physical programming unit. The method includes receiving data and arranging the data to generate a first data stream and a second data stream. The method also includes encoding the first data stream and the second data stream to generate a third data stream, and issuing a programming command sequence to write the first data stream, the second data stream and the third data stream respectively into a first physical programming unit, a second physical programming unit and a third physical programming unit of a physical programming unit set.”

The patent application was filed on January 23, 2017 (15/412,065).

Memory management method for configuring super physical units of rewritable non-volatile memory modules
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (10,579,289) developed by Lee, Ming-Yen, Miaoli County, Taiwan, for “memory management method for configuring super physical units of rewritable non-volatile memory modules, memory control circuit unit and memory storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory management method, a memory control circuit unit and a memory storage device are provided. The method includes recording use information according to each physical erasing unit of a rewritable non-volatile memory module. The method also includes configuring a plurality of super physical units. An address offset value corresponding to a first unavailable physical programming unit of a first physical erasing unit in a first super physical unit is the same as an address offset value corresponding to a first available physical programming unit of a second physical erasing unit in the first super physical unit.”

The patent application was filed on March 7, 2016 (15/063,476).

Data protecting, memory control circuit unit and memory storage
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (10,565,052) developed by Yeh, Chih-Kang, Kinmen County, Taiwan, for “data protecting method, memory control circuit unit and memory storage apparatus.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data protecting method, a memory control circuit unit and a memory storage apparatus are provided. The method includes generating a first temporary parity code group based on first data written into a first super physical unit, generating a second temporary parity code group by performing a logic operation on second data written into a second super physical unit and the first temporary parity code group, and generating an updated parity code group by performing the logic operation on the second temporary parity code group and the first data when data of the first super physical unit all become invalid data.”

The patent application was filed on March 1, 2018 (15/908,831).

Data writing method for rewritable non-volatile memory modules
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (10,564,899) developed by Yen, Chia-Han, Hsinchu, Taiwan, for “data writing method for rewritable non-volatile memory modules based on use information, memory storage device and memory control circuit unit.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data writing method, a memory storage device and a memory control circuit unit are provided. The data writing method includes: writing first data belonging to a first logical sub-unit of a first logical unit and second data belonging to a second logical sub-unit of the first logical unit to a first physical erasing unit and a second physical erasing unit respectively, recording use information corresponding to each logical unit, and executing a data arrangement operation corresponding to the first logical unit based on the use information of the first logical unit to copy the first data and the second data from the first physical erasing unit and the second physical erasing unit to a third physical erasing unit, wherein a logical address range of the second logical sub-unit follows a logical address range of the first logical sub-unit.”

The patent application was filed on May 8, 2017 (15/588,712).

Wear leveling, memory control circuit unit and memory storage
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (10,564,862) developed by Tan, Kok-Yong, Miaoli County, Taiwan, for “wear leveling method, memory control circuit unit and memory storage apparatus.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A wear leveling method for a rewritable non-volatile memory module, a memory control circuit unit, and a memory storage apparatus are provided. The rewritable non-volatile memory module includes a plurality of physical erasing units. The method includes: recording an operation value of each of the physical erasing units, recording a usage situation value of each of the physical erasing units, and selecting a first physical erasing unit and a second physical erasing unit from the physical erasing units according to the operation values of the physical erasing units and the usage situation values of the physical erasing units and copying valid data stored in the first physical erasing unit to the second physical erasing unit.”

The patent application was filed on May 25, 2018 (15/989,197).

Data protecting and memory storage
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (10,546,640) developed by Wu, Tsung-Lin, Tsui, Te-Chang, Hsinchu, Taiwan, and Lee, Chien-Fu, Yunlin County, Taiwan, for “data protecting method and memory storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data protecting method and a memory storage device are provided. The data protecting method includes reading a first string from the rewritable non-volatile memory module to obtain a data string, performing a decoding operation based on the data string to obtain block information corresponding to a plurality of physical erasing units, inputting the block information to an error checking and correcting, (ECC) circuit of the memory storage device to generate a second string, and storing the second string into the rewritable non-volatile memory module.”

The patent application was filed on May 10, 2017 (15/591,116).

Memory management, memory storage and memory control circuit
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (10,545,700) developed by Kuo, Che-Yueh, New Taipei, Taiwan, and Li, Wen-Jin, Taipei, Taiwan, for “memory management method, memory storage device and memory control circuit unit.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory management method for a memory storage device including a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: performing a data merge operation for at least one physical unit of the rewritable non-volatile memory module according to a write command from a host system, and adjusting times of performing the data merge operation according to a dispersion rate of a plurality of logical units corresponding to first data stored in at least one first-type physical unit of the rewritable non-volatile memory module.”

The patent application was filed on June 11, 2018 (16/004,444).

Decoding, memory storage and memory control circuit
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (10,534,665) developed by Lin, Yu-Hsiang, Yunlin, Taiwan, Yen, Shao-Wei, Kaohsiung, Taiwan, Yang, Cheng-Che, New Taipei, Taiwan, and Lai, Kuo-Hsin, Hsinchu, Taiwan, for “decoding method, memory storage device and memory control circuit unit.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A decoding method for a memory storage device including a rewritable non-volatile memory module is provided according to an exemplary embodiment of the invention. The method includes: reading at least one memory cells by using at least one read voltage level to obtain a codeword, performing a parity check operation on the codeword by an error checking and correcting circuit to generate a syndrome sum corresponding to the codeword, and dynamically adjusting a first parameter used by the error checking and correcting circuit in a first decoding operation based on whether the syndrome sum is less than a first threshold value and performing the first decoding operation on the codeword by the error checking and correcting circuit by using the first parameter.”

The patent application was filed on January 31, 2018 (15/884,407).

Data writing, valid data identifying, and memory storage
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (10,529,426) developed by Lin, Sung-Yao, Kuo, Yueh-Pu, New Taipei, Taiwan, and Hsiao, Yu-Min, Taipei, Taiwan, for “data writing method, valid data identifying method and memory storage apparatus.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data writing method, a valid data identifying method and a memory storage apparatus using the same are provided. The method includes receiving first data, using a first programming mode to write first sub-data of the first data into a first physical programmed unit of at least a first memory sub-module of a plurality of memory sub-modules, wherein a size of each of the first sub-data is the same as a preset size, and using a second programming mode to write remaining sub-data of the first data into a second physical programmed unit of a second memory sub-module of the plurality of memory submodules, wherein the size of the remaining sub-data is less than the preset size, and the second memory sub-module is different from a third memory sub-module of the first memory submodules which is a last memory sub-module for writing the first sub-data.”

The patent application was filed on March 2, 2018 (15/910,030).