Western Digital Assigned Twenty-Six Patents

Hybrid logical to physical address translation for non-volatile storage devices with integrated compute module
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,565,123) developed by Song, Seung-Hwan, De, Arup, Mehra, Pankaj, and O’Krafka, Brian W., San Jose, CA, for a “hybrid logical to physical address translation for non-volatile storage devices with integrated compute module.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A host compiles code to perform a set of one or more database operations on target and embeds an indication of whether the target data is randomly accessed data or sequentially accessed data. The compiled code is transmitted to the compute engine inside a memory system that maintains a first portion of memory for storing sequentially accessed data and a second portion of memory for storing randomly accessed data. The memory system (e.g. SSD) maintains reduced size L2P tables in volatile working memory by maintaining coarse L2P tables in the working memory for use with sequentially accessed data and maintaining fine L2P tables in the working memory for use with randomly accessed data. The compute engine uses the compiled code to perform the set of one or more database operations on the target data using the working memory.”

The patent application was filed on October 5, 2017 (15/726,313).

Indirection-based storage system backups using markers including sets of serial numbers associated with segments
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,565,057) developed by Singhai, Ashish, Los Altos, CA, Karamcheti, Vijay, Los Altos Hills, CA,and Narasimha, Ashwin, Los Altos, CA, for an “indirection-based storage system backups using markers including sets of serial numbers associated with segments.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data storage system comprises, a storage device having segments that are configured to store data, and storage logic coupled to the storage device that manages storage of data on the storage device using a translation table. The storage logic is executable to receive a first marker as part of a backup request, generate a second marker encapsulating a state of the storage device at a second time, calculate a difference between the first marker and the second marker, and generate a backup of data stored in the storage device based on the calculated difference between the first marker and the second marker. A garbage collection (GC) barrier may be set based on serial numbers associated with backup segments, and the garbage collection barrier may be incrementally released by releasing the garbage collection barrier for each segment after the segment has been backed up. The storage logic may also record the deletion of a storage unit from the storage device in a deletion table, and retire deleted storage mappings in the deletion table responsive to generating the backup.”

The patent application was filed on May 5, 2017 (15/587,403).

Managing phys of data storage target device
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,565,041) developed by Gerhart, Darin Edward, Oronoco, MN, Ortmeier, Nicholas Edward, and Chen, Xin, Rochester, MN, for “managing phys of a data storage target device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Embodiments of the present disclosure generally relate to managing phys of a data storage target device. In one embodiment, a method of automatically managing phys of a data storage target device by a controller of the data storage device across a link reset includes transmitting a common target phy address for a plurality of target phys during a first link reset, storing the common target phy address in a non-volatile memory of the data storage device, resetting the target phys, and transmitting the stored common target phy address for the plurality of target phys during a second link reset. In another embodiment, a method of automatically managing phys of a data storage target device by a controller of the data storage device includes matching a received host address for a plurality of target phys and configuring the plurality of target phys into a wide port for the plurality of target phys with the matched received host address.”

The patent application was filed on May 19, 2017 (15/599,931).

Storage device management
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,564,898) developed by Rao, Abhijit, Bangalore, India, and Sasidharan, Vinod, Karnataka, India, for “system and method for storage device management.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A method and apparatus for managing storage devices includes a host interface, a plurality of storage device interfaces, and a processor. The host interface is configured to communicatively couple with a host device and the plurality of storage interfaces configured to communicatively couple with storage devices. The processor is communicatively coupled to the host interface and the plurality of storage device interfaces. Further, the processor is configured to receive requests from the host device via the host interface and communicate the requests to the storage devices via the plurality of storage device interfaces. The processor is additionally configured to receive responses from the storage devices via the plurality of storage interfaces and communicate the responses to the host device via the host interface, manage a global submission queue and a global completion queue, and manage a submission queue and a completion queue for each of the storage devices.”

The patent application was filed on August 10, 2018 (16/101,169).

Storage device operations using die translation table
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,564,891) developed by Shaharabany, Amir, Kochav Yair, Israel, and Oshinsky, Hadas, Kfar Saba, Israel, for “storage device operations using a die translation table.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”In one non-limiting embodiment, a method is disclosed for performing a storage device operation on a die is provide having steps of choosing a storage device operation to perform, estimating which die is related to the storage device operation chosen to be performed and performing the storage device operation at the die based on the estimating.”

The patent application was filed on September 29, 2017 (15/721,272).

Controlling flash translation layer recycle from host
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,564,886) developed by Das Purkayastha, Saugata, Bangalore, India, for “methods and apparatus for controlling flash translation layer recycle from host.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Aspects of the disclosure provide for control of a flash translation layer (FTL) in a non-volatile memory (NVM). Disclosed methods and apparatus provide for receiving a message in the FTL, which is transmitted from a host device, and includes desired recycle ratio information that is determined by the host where the ratio is a number of host writes to a number of recycle writes to be performed by the FTL. Based on the recycle ratio information, the FTL determines a target recycle ratio and performs recycling of memory blocks in the NVM based on the determined target recycle ratio. In this manner, the host device is able to exert control over the recycle ratio utilized in the FTL via a transmitted message, which allows the recycle ratio to be more adaptive to host write conditions known to the host device, but not known in the SSD.”

The patent application was filed on February 20, 2018 (15/900,673).

Dynamic allocation to host of memory device controller memory ressources
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,564,872) developed by Benisty, Shay, Beer Sheva, Israel, for “system and method for dynamic allocation to a host of memory device controller memory ressources.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Systems and methods for a non-volatile memory (NVM) system to allocate controller memory buffer resources to multiple host functions based on host input are disclosed. The NVM system may include a NVM controller configured to advertise total available controller buffer resources to a host. The NVM system includes host writable controller buffer allocation registers for receiving host selected amounts of available controller buffer resources, where a physical function on the host selects a portion of the buffer resources for itself and also selects portions of NVM system controller buffer resources for each other of the secondary, or virtual, host functions also in communication with the NVM system. In this manner, a host in a non-volatile memory express (NVMe) system may dynamically designate controller buffer resources for itself and all other hosts of the NVM system rather than relying on a static NVM system default distribution of controller buffer resources.”

The patent application was filed on June 29, 2018 (16/023,767).

QoS over NVMe virtualization platform using adaptive command fetching
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,564,857) developed by Benisty, Shay, Be’er Sheva, Israel, Walsh, James, Santa Clara, CA, and Koul, Rajesh, San Jose, CA, for “system and method for QoS over NVMe virtualization platform using adaptive command fetching.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Systems and methods for quality of service (QoS) using adaptive command fetching are disclosed. NVM Express (NVMe) implements a paired submission queue and completion queue mechanism, with host software on the host device placing commands into the submission queue. The memory device processes the commands through various phases including fetching, processing, posting a completion message, and sending an interrupt to the host. NVMe also includes an NVMe virtualization environment, which uses a subsystem with multiple controllers to provide virtual or physical hosts direct I/O access. QoS may be used so that the NVMe processes in the virtualization environment receive sufficient resources. In particular, bandwidth assigned to a submission queue may be considered when processing of commands, such as fetching of commands). In the event that the bandwidth assigned to the submission queue is exceeded, the processing of the commands, (such as the fetching of the commands) may be delayed.”

The patent application was filed on November 13, 2017 (15/810,632).

Locality detection to identify read or write streams in memory device
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,564,853) developed by Linkovsky, Vitali, Benisty, Shay, Beer Sheva, Israel, Guthrie, William, Santa Cruz, CA, and Virani, Scheheresade, Frisco, TX, for “system and method for locality detection to identify read or write streams in a memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Systems and methods for determining locality of an incoming command relative to previously identified write or read streams is disclosed. NVM Express (NVMe) implements a paired submission queue and completion queue mechanism, with host software on the host device placing commands into multiple submission queues. The memory device fetches the commands from the multiple submission queues, which results in the incoming commands being interspersed. In order to determine whether the incoming commands should be assigned to previously identified read or write streams, the locality of the incoming commands relative to the previously identified read or write streams is analyzed. One example of locality is proximity in address space. In response to determining locality, the incoming commands are assigned to the various streams.”

The patent application was filed on April 26, 2017 (15/497,547).

HAMR thermal sensor with fast response time
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,564,053) developed by Contreras, John T., Palo Alto, CA, Huang, Lidu, Danville, CA, Ren, Shen, Union City, CA, Schreck, Erhard, San Jose, CA, and Zakai, Rehan Ahmed, San Ramon, CA, for a “HAMR thermal sensor with fast response time.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Embodiments disclosed herein generally relate to a method for monitoring optical power in a HAMR device. In one embodiment, the method includes enhancing a thermal sensor bandwidth through advanced electrical detection techniques. The advanced electrical detection techniques include obtaining calibration waveform data for a thermal sensor by calibrating the thermal sensor, obtaining real-time waveform data for the thermal sensor that may deviate from the calibration waveform data, updating the calibration waveform data to include the real-time waveform data, repeating obtaining real-time waveform data and updating the calibration waveform data during writing operations. By updating the calibration waveform data, the bandwidth of the thermal sensor is determined by a fixed sampling time interval, and the thermal sensor rise time to steady state would not be a limitation to its response time.”

The patent application was filed on December 21, 2018 (16/229,855).

Cloud-based management of access to data storage system on local network
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,560,528) developed by Rachabathuni, Sailesh, Santa Clara, CA, and Gaillard, Jonathan, San Francisco, CA, for a “cloud-based management of access to a data storage system on a local network.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Systems and methods are disclosed for managing access between a data storage server and a client that are on the same local network. Access is managed using a cloud service that is remote from both the data storage server and the client requesting access to the server. The cloud-based management of local connections described herein simplifies the process of connecting to a data storage server on a local network from a client program or device. Connections are authorized based on the use of a local code. The local code is generated by the cloud service and includes a concatenation of a device identifier associated with the data storage server and a time-varying value, such as a timestamp.”

The patent application was filed on August 29, 2017 (15/690,068).

Storage system and method for die-based data retention recycling
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,559,329) developed by Yuan, Jingfeng, Higgins, James M., and Whaley, Jeff, Irvine, CA, for “storage system and method for die-based data retention recycling.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”The subject technology performs the following in a storage system including memory dies, where each memory die includes its own temperature sensor. The subject technology determines a temperature of each of the memory dies based on a temperature reading from each memory die’s temperature sensor. The subject technology determines whether data is hot data or cold data, where hot data is more likely to be changed after it is written than cold data. In response to determining that the data is hot data, the subject technology stores the data in a memory die with a relatively higher temperature than another one of the memory dies. Further, in response to determining that the data is cold data, the subject technology stores the data in a memory die with a relatively cooler temperature than another one of the memory dies.”

The patent application was filed on September 26, 2018 (16/143,271).

Storage device with rapid overlay access
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,558,576) developed by Gopalakrishnan, Raghavendra Das, and Dixit, Pankaj, Bangalore, India, for a “storage device with rapid overlay access.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”An example of a system includes a host interface, a set of non-volatile memory cells, and one or more control circuits coupled to the host interface and coupled to the set of non-volatile memory cells. The one or more control circuits include a portion of a Random Access Memory (RAM) configured as an overlay RAM. The one or more control circuits are configured to transfer overlay code to the overlay RAM via the host interface.”

The patent application was filed on January 22, 2018 (15/876,785).

Storage system and method for namespace reservation in multi-queue single-controller environment
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,558,376) developed by Hahn, Judah Gamliel, Ofra, Israel, and Benisty, Shay, Beer Sheva, Israel, for “storage system and method for namespace reservation in a multi-queue single-controller environment.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A storage system and method for namespace reservation in a multi-queue single-controller environment are provided. In one embodiment, a method for access control in a memory is performed in a storage system comprising a memory and a controller in communication with a plurality of hosts, wherein each host comprises its own set of input-output queues but only one host comprises an admin queue. The method comprises receiving a mapping that restricts access to portions of the memory to specific ones of the plurality of hosts, wherein the mapping is generated by the host that comprises the admin queue, and restricting access to the portions of the memory based on the mapping. Other embodiments are provided.”

The patent application was filed on June 28, 2018 (16/021,813).

Memory station for automatically backing up data and charging mobile devices
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,554,796) developed by Ziv, Aran, Foster City, CA, Muraleedha, Anurag Chelamchirayil, Santa Clara, CA, and Hakoun, Eyal, Sunnyvale, CA, for a “memory station for automatically backing up data and charging mobile devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Disclosed herein are memory stations that are configured to charge a mobile device, to receive data for storage from the mobile device, and to transmit a trigger signal to the mobile device responsive to the beginning of a charge cycle to initiate the backup process. The disclosed systems and methods include starting a backup application on a mobile device responsive to a trigger signal. The trigger signal is generated and transmitted wirelessly by a memory station responsive to the memory station detecting the beginning of a charging cycle. In this way, the mobile device can automatically execute a backup program or application without user intervention. The disclosed memory stations and related methods beneficially enable seamless data backup while charging a mobile device. This can be accomplished with no user intervention.”

The patent application was filed on November 1, 2017 (15/801,250).

Data storage device encoding and interleaving codewords to improve trellis sequence detection
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,554,225) developed by Chen, Yiming, Rancho Santa Margarita, CA, and Krishnan, Anantha Raman, Foothill Ranch, CA, for “data storage device encoding and interleaving codewords to improve trellis sequence detection.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data storage device is disclosed comprising a storage medium. Input data is encoded according to at least one channel code constraint to generate first data and second data. The first data is encoded into a first codeword, and the second data is encoded into a second codeword, wherein a first code rate of the first codeword is less than a second code rate of the second codeword. The first codeword and the second codeword are interleaved to generate an interleaved codeword, and the interleaved codeword is written to the storage medium.”

The patent application was filed on August 20, 2018 (16/105,689).

Data storage device encoding and interleaving codewords to improve trellis sequence detection
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,554,221) developed by Chen, Yiming, Rancho Santa Margarita, CA, for “data storage device encoding and interleaving codewords to improve trellis sequence detection.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data storage device is disclosed comprising a storage medium. First data is encoded into a first codeword comprising a plurality of i-bit symbols, and second data is encoded into a second codeword comprising a plurality of j-bit symbols, wherein i is different than j and a first code rate of the first codeword is less than a second code rate of the second codeword. The first codeword and the second codeword are symbol interleaved to generate an interleaved codeword, and the interleaved codeword is written to the storage medium.”

The patent application was filed on August 23, 2018 (16/110,493).

Data storage device calibrating data density based on amplitude-inverted or time-inverted read signal
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,553,247) developed by Nichols, Mark A., and Eaton, Robert E., San Jose, CA, for a “data storage device calibrating data density based on amplitude-inverted or time-inverted read signal.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data storage device is disclosed comprising a head actuated over a disk. A test pattern is read from a first part of the disk to generate a first read signal that is sampled to generate a first sequence of signal samples. The test pattern is read from a second part of the disk to generate a second read signal that is sampled to generate a second sequence of signal samples. A third sequence of signal samples is generated by at least one of amplitude-inverting the second sequence of signal samples, time-inverting the second sequence of signal samples, and amplitude-inverting and time-inverting the second sequence of signal samples. A quality metric is generated based on the first sequence of signal samples and the third sequence of signal samples, and a data density of the disk is configured based on the quality metric.”

The patent application was filed on May 30, 2018 (15/993,209).

Near-field transducer for HAMR
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,553,241) developed by Vossough, Kris, Redwood City, CA, Zhang, Xiaokai, Dublin, CA, Kirakosian, Armen, Walnut Creek, CA, Wang, Jinwen, Pleasanton, CA, Chen, Tsung Yuan, San Ramon, CA, and Hu, Yufeng, Fremont, CA, for a “Near-field transducer (NFT) for a heat assisted magnetic recording (HAMR) device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A method and system provides a near-field transducer (NFT) for a heat assisted magnetic recording (HAMR) transducer. The method and system include forming the disk of the NFT and forming the pin of the NFT. The disk is formed from a first material. The pin is formed from a second material different from the first material. The pin contacts the disk. At least a portion of the pin is between the disk and an air-bearing surface (ABS) location.”

The patent application was filed on January 2, 2018 (15/859,922).

Optimizing data block size for deduplication
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,552,379) developed by Ram, Tamir, Sunnyvale, CA, for an “optimizing data block size for deduplication.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Provided herein is technology relating to data deduplication and particularly, but not exclusively, to methods and systems for determining an efficiently optimal size of data blocks to use for backing up a data source. Also provided herein are systems for identifying duplicate data in data backup applications.”

The patent application was filed on April 12, 2017 (15/486,224).

Reducing write-backs to memory by controlling age of cache lines in lower level cache
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,552,325) developed by Kamruzzaman, Md, Cupertino, CA, for “reducing write-backs to memory by controlling the age of cache lines in lower level cache.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A method and apparatus for reducing write-backs to memory is disclosed herein. The method includes determining whether a read/write request entering a lower level cache is a cache line containing modified data, and responsive to determining that the read/write request is not a cache line containing modified data, manipulating age information of the cache line to reduce a number of write-backs to memory.”

The patent application was filed on April 20, 2018 (15/958,563).

Controlling PCIe direct attached nonvolatile memory storage
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,552,284) developed by Skandakumaran, Krishanth, Los Gatos, CA, Medapati, Arun Kumar, Andhra Pradesh, India, Namala, Sri Rama, San Jose, CA, Narasimha, Ashwin, Sunnyvale, CA, and Kumar B, Ajith, Bangalore, India, for “system and method for controlling PCIe direct attached nonvolatile memory storage subsystems.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Techniques for controlling power on a PCIe direct attached non-volatile memory storage system are disclosed. In one particular embodiment, the techniques may be realized as a method for controlling power including providing power to a memory attached via the PCIe interface, monitoring a state of the attached memory, determining whether a new operation to be implemented on the attached memory would cause the power provided to the memory to exceed a preset threshold, and stalling execution of the new operation on the attached memory when it is determined that the new operation would exceed the preset threshold while continuing execution of preexisting operations on the attached memory.”

The patent application was filed on April 3, 2017 (15/478,155).

Hidden diagnostic partition
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,552,264) developed by Lemberg, Alexander, Kfar Saba, Israel, and Sela, Rotem, Haifa, Israel, for a “hidden diagnostic partition.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A storage device with a memory may have a hidden diagnostic partition that can only be accessed during debug or diagnostic mode. Debug or diagnostic mode allows a host device to access the debug or diagnostic analysis, (e.g. error logs) stored in the hidden diagnostic partition. By default, the hidden diagnostic partition is invisible to the host. When accessed through a triggering event, such as a vendor specific command, (VSC), the hidden diagnostic partition can be used to report debug and error events.”

The patent application was filed on September 27, 2017 (15/717,494).

Recovery combining hard decoding, soft decoding and artificial codeword generation
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,552,259) developed by Jacobvitz, Adam Noah, Mountain View, CA, Kathawala, Gulzar Ahmed, Fremont, CA, Stoev, Kroum Stanimirov, Pleasanton, CA, and Wu, Bin, Fremont, CA, for “recovery combining hard decoding, soft decoding and artificial codeword generation.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”The present disclosure, in various embodiments, describes technologies and techniques for use by a data storage controller for decoding codewords during an error correction read recovery process. In illustrative examples, an iterative procedure exploits artificial codewords generated using information obtained from a NAND or other non-volatile memory (NVM) in a previous sense operation. That is, procedures are described that use information obtained in one stage of read recovery to facilitate a subsequent stage to reduce the need to perform additional NAND senses. In one example, information obtained from a sense operation performed for an initial hard bit decode is used in subsequent soft bit decodes. Moreover, iterative decoding procedures are provided that progressively increase correction strength. The procedures may alternate between hard and soft reads while using syndrome weight to determine a failed bit code gradient for identifying the sensing voltage for a next hard sense.”

The patent application was filed on March 15, 2018 (15/922,793).

Storage of neural networks
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,552,251) developed by Qin, Minghai, Vucinic, Dejan, and Sun, Chao, San Jose, CA, for a “storage of neural networks.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Disclosed include a device and a method for storing a neural network. The device includes a plurality of memory cells configured to store weights of the neural network. The plurality of memory cells may include one or more faulty cells. The device further includes a processor coupled to the plurality of memory cells. The processor is configured to construct the neural network based on a structure of the neural network and a subset of the weights stored by the plurality of memory cells. The subset of the weights may exclude another subset of the weights stored by one or more memory cells comprising the one or more faulty cells.”

The patent application was filed on December 12, 2017 (15/839,521).

Multi-tier scheme for logical storage management
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,552,055) developed by Liu, Haining, Irvine, CA, Pavlenko, Yuriy, Mission Viejo, CA, and Artnak, Jr., George G., Yorba Linda, CA, for a “multi-tier scheme for logical storage management.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A storage device may include a controller and a memory array including a plurality of dies arranged into a plurality of channels. In some examples, the controller may be configured to define, from the memory array, a plurality of die-sets based on respective chip enable lines associated with the plurality of dies, wherein each die-set of the plurality of die-sets includes at least one die from each of the plurality of channels, define, from a selected die-set of the plurality of die-sets, a plurality of blocksets, wherein each blockset includes a block from each die of the selected die-set, receive a unit of data to be stored, and issue commands that cause the unit of data to be stored in blocks of a selected blockset of the plurality of blocksets.”

The patent application was filed on March 29, 2019 (16/370,811).