Cadence Design Systems Assigned Patent

Cadence Design Systems, Inc., San Jose, CA, has been assigned a patent (10,579,470) developed by MacLaren, John M., and Olson, Carl Nels, Austin, TX, for an “address failure detection for memory devices having inline storage configurations.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Various embodiments provide for a memory controller capable of detecting an error on addressing, (address error or address fault) of memory commands for a memory device implementing an inline storage configuration of primary data with associated error checking data. According to some embodiments, the memory controller indicates that an address error of a particular memory command has occurred, (or likely occurred) by detecting when a plurality of data errors is produced by a plurality of error checks performed on primary data resulting from the particular memory command. Various embodiments described herein allow both single-bit error detection and correction, and address protection to exist in a memory solution implementing an inline error checking data storage configuration, such as inline ECC storage configuration.”

The patent application was filed on July 26, 2018 (16/046,927).