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Intel Assigned Twelve Patents on Storage

Providing wireless storage and processing capabilities, multi-node storage operation, ferroelectric based memory cell with non-volatile retention, de-dupe-based data security, dynamically allocating storage capacity for differen storage, storage appliance for processing of FaaS, low-latency interface to storage, protecting data in asymmetric storage volume, combining logical-to-physical address table updates in single write operation, storage device having improved write uniformity stability, throttling rate at which commands are accepted in storage device, multiple storage devices implemented using common connector

Provide wireless storage and processing capabilities
Intel Corporation, Santa Clara, CA, has been assigned a patent (10,582,017) developed by Zhu, Jiangfang Olena, Yepes, Ana, Lahiri, Sayan, Qui, Bo, Hillsboro, OR, Daniel, Kevin, Tigard, OR, and Zhang, Guodong, Portland, OR, for “techniques to provide wireless storage and processing capabilities.

The abstract of the patent published by the U.S. Patent and Trademark Office states: Embodiments may be generally directed to techniques to utilize a protocol adaption layer, (PAL) extension based on the bus protocol to enable a wireless transfer of data between a persistent storage device and a remote device and communicate, via a transceiver, the data as radio-frequency, (RF) signals between the persistent storage device and the remote device utilizing the PAL extension.

The patent application was filed on December 24, 2015 (15/778,314).

Multi-node storage operation
Intel Corporation, Santa Clara, CA, has been assigned a patent (10,581,968) developed by Larsen, Steen, Portland, OR, Guim Bernat, Francesc, Barcelona, Spain, Doshi, Kshitij A., Tempe, AZ, and Schmisseur, Mark A., Phoenix, AZ, for a “multi-node storage operation.

The abstract of the patent published by the U.S. Patent and Trademark Office states: A technology is described for performing a multi-node storage operation. An example networked memory storage group coupled to a plurality of computing nodes through s network fabric can be configured to receive a transaction detail message from a master computing node that includes a transaction identifier and transaction details for a multi-node storage operation. Thereafter, storage operation requests that include the transaction identifier may be received from computing nodes assigned storage operation tasks associated with the multi-node storage operation. The networked memory storage group may be configured to determine that storage operations for the multi-node storage operation have been completed and send a message to the master computing node indicating a completion state of the multi-node storage operation.

The patent application was filed on April 1, 2017 (15/477,076).

Ferroelectric based memory cell with non-volatile retention
Intel Corporation, Santa Clara, CA, has been assigned a patent (10,573,385) developed by Morris, Daniel H., Hillsboro, OR, Avci, Uygar E., and Young, Ian A., Portland, OR, for a “ferroelectric based memory cell with non-volatile retention.

The abstract of the patent published by the U.S. Patent and Trademark Office states: Described is an apparatus which comprises: a first access transistor controllable by a write word-line, (WWL), a second access transistor controllable by a read word-line, (RWL), and a ferroelectric cell coupled to the first and second access transistors, wherein the ferroelectric cell is programmable via the WWL and readable via the RWL. Described is a method which comprises: driving a WWL, coupled to a gate terminal of a first access transistor, to cause the first access transistor to turn on, and driving a WBL coupled to a source/drain terminal of the first access transistor, the driven WBL to charge or discharge a storage node coupled to the first access transistor when the first access transistor is turned on, wherein the ferroelectric cell is coupled to the storage node and programmable according to the charged or discharged storage node.

The patent application was filed on May 28, 2015 (15/567,942).

Deduplication-based data security
Intel Corporation, Santa Clara, CA, has been assigned a patent (10,558,377) developed by Cheriton, David R., Palo Alto, CA, for a “deduplication-based data security.

The abstract of the patent published by the U.S. Patent and Trademark Office states: Providing data security includes: in response to a request to write data content to a storage, generating encrypted data content based on the data content, attempting to obtain a reference to the encrypted data content in the storage, in the event that the reference to the encrypted data content is obtained, modifying a translation line to refer to the reference to the encrypted data content in the storage, and in the event that the reference to the encrypted data content is not obtained: storing the encrypted data content at a new location, obtaining a reference to the encrypted data content stored at the new location, and modifying the translation line to refer to the reference to the encrypted data content stored at the new location.

The patent application was filed on October 16, 2017 (15/785,282).

Dynamically allocating data storage capacity for different data storage
Intel Corporation, Santa Clara, CA, has been assigned a patent (10,554,391) developed by Miller, Steven, Livermore, CA, and Dormitzer, Paul, Acton, MA, for “technologies for dynamically allocating data storage capacity for different data storage types.

The abstract of the patent published by the U.S. Patent and Trademark Office states: Technologies for allocating data storage capacity on a data storage sled include a plurality of data storage devices communicatively coupled to a plurality of network switches through a plurality of physical network connections and a data storage controller connected to the plurality of data storage devices. The data storage controller is to determine a target storage resource allocation to be used by one or more applications to be executed by one or more sleds in a data center, determine data storage capacity available for each of a plurality of different data storage types on the data storage sled, wherein each data storage type is associated with a different level of data redundancy, determine an amount of data storage capacity for each data storage type to be allocated to satisfy the target storage resource allocation, and adjust the amount of data storage capacity allocated to each data storage type.

The patent application was filed on December 28, 2017 (15/856,220).

Storage appliance for processing of FaaS
Intel Corporation, Santa Clara, CA, has been assigned a patent (10,545,925) developed by Trika, Sanjeev N., Khan, Jawad B., Portland, OR, and Wysocki, Piotr, Gdansk, Poland, for a “storage appliance for processing of functions as a service, (FaaS).

The abstract of the patent published by the U.S. Patent and Trademark Office states: Examples may include a storage appliance having a mass storage device and a compute engine communicating peer-to-peer with each other, with the compute engine including a programmable logic component to execute a function to read data from the at least one storage device, process the data, and write data to the at least one storage device.

The patent application was filed on June 6, 2018 (16/001,398).

Low-latency interface to data storage
Intel Corporation, Santa Clara, CA, has been assigned a patent (10,542,333) developed by Miller, Steven C., Livermore, CA, for “technologies for a low-latency interface to data storage.

The abstract of the patent published by the U.S. Patent and Trademark Office states: Technologies for a low-latency interface with data storage of a storage sled in a data center are disclosed. In the illustrative embodiment, a storage sled stores metadata including the location of data in a storage device in low-latency non-volatile memory. When accessing data, the storage sled may access the metadata on the low-latency non-volatile memory and then, based on the location determined by the access to the metadata, access the location of the data in the storage device. Such an approach results in only one access to the data storage in order to read the data instead of two.

The patent application was filed on December 30, 2016 (15/396,028).

Protecting data in asymmetric storage volume
Intel Corporation, Santa Clara, CA, has been assigned a patent (10,540,505) developed by Boyd, James A., Hillsboro, OR, Juenemann, Dale J., North Plains, OR, and Royer, Jr., Robert J., Portland, OR, for “technologies for protecting data in an asymmetric storage volume.

The abstract of the patent published by the U.S. Patent and Trademark Office states: Technologies for protecting data in an asymmetric volume, (ASV) that includes a first storage device that supports device-based encryption and a second storage device that does not support device-based encryption. In embodiments the technologies enable disparate capabilities of the storage devices in an ASV to be exposed to a user. When a complete copy of targeted data identified by a user input for encrypted storage is not present on the first storage device, at least a portion of the targeted data stored on the second storage device is rewritten to the first storage device. When a complete copy of the targeted data is stored on the first storage device, one or more security operations are performed to obfuscate or erase any portion of the targeted data stored on the second storage device.

The patent application was filed on September 29, 2017 (15/721,554).

Combining logical-to-physical address table updates in single write operation
Intel Corporation, Santa Clara, CA, has been assigned a patent (10,528,463) developed by Li, Peng, Hillsboro, OR, Ramalingam, Anand S., Beaverton, OR, Lui, William K., and Trika, Sanjeev N., Portland, OR, for “technologies for combining logical-to-physical address table updates in a single write operation.

The abstract of the patent published by the U.S. Patent and Trademark Office states: Technologies for combining logical-to-physical address updates include a data storage device. The data storage device includes a non-volatile memory to store data and a logical to physical, (L2P) table indicative of logical addresses and associated physical addresses of the data. Additionally, the data storage device includes a volatile memory to store one or more bins. Each bin is indicative of a subset of entries in the L2P table. Further, the data storage device includes a controller to allocate a bin in the volatile memory, write a plurality of updates to a subset of entries of the L2P table to the bin, and write the bin to the L2P table in a single write operation. Other embodiments are also described and claimed.

The patent application was filed on September 28, 2016 (15/278,837).

Storage device having improved write uniformity stability
Intel Corporation, Santa Clara, CA, has been assigned a patent (10,528,462) developed by Ramalingam, Anand S., Beverton, OR, for a “storage device having improved write uniformity stability.

The abstract of the patent published by the U.S. Patent and Trademark Office states: A machine readable storage medium containing program code that when processed by a processor causes a method to be performed a method is described. The method includes executing a wear leveling routine by servicing cold data from a first queue in a non volatile storage device to write the cold data. The method also includes executing a garbage collection routing by servicing valid data from a second queue in the non volatile storage device to write the valid data. The method also includes servicing host write data from a third queue in the non volatile storage device to write the host write data wherein the first queue remains fixed and is serviced at a constant rate so that a runtime size of the third queue is not substantially affected by the wear leveling routine.

The patent application was filed on September 26, 2016 (15/276,696).

Throttling rate at which commands are accepted in storage device
Intel Corporation, Santa Clara, CA, has been assigned a patent (10,521,121) developed by Carlton, David B., Oakland, CA, Guo, Xin, San Jose, CA, and Du, Yu, Santa Clara, CA, for “apparatus, system and method for throttling a rate at which commands are accepted in a storage device.

The abstract of the patent published by the U.S. Patent and Trademark Office states: Provided are an apparatus, system and method for apparatus, system and method for throttling an acceptance rate for adding host Input/Output, (I/O) commands to a buffer in a non-volatile memory storage device. Information is maintained on an input rate at which I/O commands are being added to the buffer and information is maintained on an output rate at which I/O commands are processed from the buffer to apply to execute against the non-volatile memory. A determination is made of a current level of available space in the buffer and an acceptance rate at which I/O commands are added to the buffer from the host system to process based on the input rate, the output rate, the current level of available space, and an available space threshold for the buffer to maintain the buffer at the available space threshold. I/O commands are added to the buffer to process based on the acceptance rate. The I/O commands are accessed from the buffer to process to execute against the non-volatile memory.

The patent application was filed on December 29, 2016 (15/394,653).

Multiple storage devices implemented using common connector
Intel Corporation, Santa Clara, CA, has been assigned a patent (10,509,759) developed by Willis, Daniel S., and Constantine, Anthony M., Portland, OR, for “multiple storage devices implemented using a common connector.

The abstract of the patent published by the U.S. Patent and Trademark Office states: Provided are an apparatus, system, and method relating to detecting, during a system boot operation, whether a device arranged to implement a first bus interface protocol is coupled to a system through a connector. A bus clock is programmed to be off in response to detection of no device implementing the first bus interface protocol being coupled to the system through the connector. After the bus clock is programmed to be off, a buffer is reprogrammed to assume that the connector implements a second bus interface protocol coupled to a storage device. After reprogramming the buffer, the apparatus, system, and method detect whether a device arranged to implement the second bus interface protocol is coupled to the connector, and the device arranged to implement the second bus interface protocol is initialized in response to detection that the device is coupled to the connector. Other embodiments are described and claimed.

The patent application was filed on March 31, 2017 (15/476,882).