R&D: Impact of Low Temperature on TSG Vt Shift During Erase Cycling of 3D NAND Flash

IEEE Xplore has published, in 2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA) proceedings, an article written by Da Li, Peking University, Beijing, China,100871, Lei Jin, Liang Yan, Xinlei Jia, University of Chinese Academy of Sciences, Beijing, China,100049, Jianquan Jia, Yali Song, An Zhang, Feng Xu, Yangtze Memory Technologies Co., Ltd., Wuhan, China 430205, Wei Hou, Zongliang Huo, University of Chinese Academy of Sciences, Beijing, China,100049, and Jianhua Feng, Peking University, Beijing, China,100871.

Abstract: “Charge trapping memory (CTM) endurance has been widely investigated in recent years. Most studies are focused on array cell Vt instabilities, which is originated from charge trapping/detrapping in cell tunnel oxide and interface traps. Our previous works demonstrate erase only cycling induced TSG shift in 3D NAND flash. In this work, it is found that the erase cycling induced TSG VT shift is temperature dependent. TSG Vt shift under low temperature is obviously worse than room and high temperature. TCAD simulation shows hot carrier induced by channel potential gradient is more significant under low temperature during erase operation due to low mobility. The stability of TSG cell Vt is related with both temperature and TSG bias voltage during erase according to the experiments and simulation.“