Western Digital Technologies Assigned Twenty Two Patents

Magnetic write head for providing spin-torque-assisted write field enhancement
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,546,603) developed by Olson, James Terrence, Santa Cruz, CA, Hoshiya, Hiroyuki, Odawara, Japan, Goncharov, Alexander, Morgan Hill, CA, Shiimoto, Masato, Fujisawa, Japan, and Sugiyama, Mikito, Odawara, Japan, for a “magnetic write head for providing spin-torque-assisted write field enhancement.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Disclosed herein are magnetic write heads and hard disk drives comprising such magnetic write heads. A magnetic head comprises a magnetic pole, a first shield separated from the magnetic pole at an air-bearing surface,(ABS) of the magnetic head, a magnetic layer disposed between the magnetic pole and the first shield, wherein the magnetic layer comprises at least of iron, cobalt, or nickel, a first non-magnetic layer disposed between the magnetic pole and the magnetic layer, and a second non-magnetic layer disposed between the magnetic layer and the first shield, wherein the magnetic layer is the only magnetic layer at the ABS that is between the main pole and the first shield that is not adjacent to the main pole or the first shield.”

The patent application was filed on June 13, 2019 (16/440,922).

Using file system extended attributes to recover databases in hierarchical file
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,545,829) developed by Hellwege, Stephen Allen, Ladera Ranch, CA, Rachabathuni, Sailesh, Santa Clara, CA, Baughman, Samuel Kevin, Anaheim, CA, Ribeiro, Gabriel, and Gaillard, Jonathan, San Francisco, CA, for “using file system extended attributes to recover databases in hierarchical file systems.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Systems and methods are disclosed for reconstructing a file hierarchy by scanning attributes of stored files. Stored files can have a file hierarchy that is maintained in a database stored on a storage device. The files can be stored as objects on the device using a flat file structure. The file database provides the file hierarchy. The systems and methods disclosed herein store information in file system extended attributes for individual storage files such that the database can be reconstructed by scanning the storage files, using values in the extended attributes to recreate the hierarchical database.”

The patent application was filed on August 29, 2017 (15/690,114).

Soft-decision input generation for data storage
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,545,819) developed by Lu, Guangming, Irvine, CA, for a “soft-decision input generation for data storage systems.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”An error management system for a data storage device can generate soft-decision log-likelihood ratios, (LLRs) using multiple reads of memory locations. 0-to-1 and 1-to-0 bit flip count data provided by multiple reads of reference memory locations can be used to generate probability data that is used to generate possible LLR values for decoding target pages. Possible LLR values are stored in one or more look-up tables.”

The patent application was filed on December 29, 2014 (14/584,326).

Monitoring non-volatile memory read errors using background media scan
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,545,810) developed by Barndt, Richard David, San Diego, CA, Chang, Hung-min, Irvine, CA, Cometti, Aldo Giovanni, San Diego, CA, Lo, Jerry, Hacienda Heights, CA, and Yeh, Hung-Cheng, Irvine, CA, for “method and apparatus for monitoring non-volatile memory read errors using background media scan.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Aspects of the disclosure provide a method and an apparatus that perform a background media scan, (BGMS) with improved efficiency. In particular, the disclosed BGMS processes can monitor data retention performance of a large capacity solid state drive, (SSD) without significantly increasing scanning overhead by scanning only some sample pages of a memory block.”

The patent application was filed on December 22, 2016 (15/388,603).

Managing I/O operations in storage network
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,540,323) developed by Blagojevic, Filip, Emeryville, CA, and Guyot, Cyril, San Jose, CA, for “managing I/O operations in a storage network.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Various aspects for managing input/output operations in a storage network are described. For instance, a method may include applying a hash function on a target data object to calculate a hash key for the target data object and identifying a target storage bucket for the target data object based on the hash key and a hash table map. The method may further include reading a data object key for a data object stored in the target storage bucket and comparing the data object key and the hash key to determine a match. The method may also include determining that the data object is the target data object if the data object key and the hash key match and reading the target data object from the target storage bucket when there is a match. Some methods can be performed using a single remote direct access request.”

The patent application was filed on May 30, 2017 (15/608,945).

Copy on write on SSD
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,540,106) developed by Dewitt, Dylan Mark, Espeseth, Adam Michael, Mccambridge, Colin Christopher, and Dreyer, David George, Rochester, MN, for “system and method for copy on write on an SSD.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Techniques for improved copy on write functionality within an SSD are disclosed. In some embodiments, the techniques may be realized as a method for providing improved copy on write functionality within an SSD including providing, in memory of a device, an indirection data structure. The data structure may include a master entry for cloned data, the master entry having a reference to one or more indexes and a clone entry for the cloned data, the cloned entry having at least one of: a reference to a master index, a reference to a next index, and a value indicating an end of a data structure. The techniques may include traversing, using a computer processor, one or more copies of the cloned data using one or more of the references.”

The patent application was filed on January 22, 2018 (15/876,245).

Mapping-based wear leveling for non-volatile memory
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,540,100) developed by Gholamipour, Amir Hossein, Mishra, Chandan, Irvine, CA, and Helmick, Daniel, Broomfield, CO, for a “mapping-based wear leveling for non-volatile memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Apparatuses, systems, and methods are disclosed for mapping-based wear leveling for non-volatile memory. An apparatus may include one or more non-volatile memory elements, and a controller. A controller may maintain a logical-to-physical mapping for converting logical addresses to physical addresses. A logical-to-physical mapping may include a translation table that associates groups of logical addresses with groups of physical addresses, and one or more mathematical mappings. A mathematical mapping for a group of logical addresses may associate individual logical addresses within the group of logical addresses with individual physical addresses within a corresponding group of physical addresses. A controller may change at least one mathematical mapping. A controller may move data based on at least one changed mapping.”

The patent application was filed on April 10, 2018 (15/949,976).

ECC and raid-type decoding
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,536,172) developed by Ilani, Ishai, Dolev, Israel, Alrod, Idan, Herzliya, Israel, Sharon, Eran, Rishon Lezion, Israel, and Ghaly, Mai, San Jose, CA, for “ECC and raid-type decoding.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A device includes a memory and a controller coupled to the memory. The controller is configured to read a codeword from a physical location of the memory. The controller is configured to write an inverse bit string to the physical location of the memory, the inverse bit string based on the codeword. The controller is configured to read a representation of the inverse bit string from the physical location of the memory. The controller is further configured to designate one or more bits of the codeword as one or more erased bits based on the codeword and the representation of the inverse bit string.”

The patent application was filed on November 20, 2017 (15/817,535).

String-based erase verify to create partial good blocks
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,535,411) developed by Dunga, Mohan, Santa Clara, CA, Khandelwal, Anubhav, San Jose, CA, Chen, Changyuan, San Ramon, CA, and Ray, Biswajit, Huntsville, AL, for “system and method for string-based erase verify to create partial good blocks.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Systems and methods for string-based erase verify to create partial good blocks are disclosed. A block in non-volatile flash memory may include multiple strings. In practice, one string may be slower to erase than other strings. In analyzing the strings, the memory device may iteratively analyze the strings to verify as erased. As one example, the iterations are modified by changing which strings are erased in the subsequent iterations, (e.g., only the strings that fail the erase verify). As another example, a predetermined number of iterations are performed after a majority of the strings are verified as erased. In this way, the strings verified as erased need not undergo more deep erasing, which may damage the strings. Further, if fewer than all of the strings are verified as erased, the memory device may designate the block as a partially good block.”

The patent application was filed on May 26, 2017 (15/606,931).

Host bus adaptor with configurable interface
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,534,738) developed by Ranjan, Kumar, and Koul, Sunny, Bangalore, India, for a “host bus adaptor with configurable interface.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A system includes a host interface, a storage interface, and one or more control circuits coupled to the host interface and coupled to the storage interface. The one or more control circuits include a common set of registers configured to maintain first entries according to a first storage protocol for first storage devices connected to the storage interface and to maintain second entries according to a second storage protocol for second storage devices connected to the storage interface.”

The patent application was filed on January 17, 2018 (15/873,395).

Random number generator by superparamagnetism
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,534,579) developed by Braganca, Patrick M., San Jose, CA, Katine, Jordan A., Mountain View, CA, Li, Yang, San Jose, CA, Robertson, Neil L., Palo Alto, CA, Wang, Qingbo, Beijing, China, and Xi, Haiwen, San Jose, CA, for a “random number generator by superparamagnetism.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A system according to one embodiment includes a pinned layer, a spacer layer above the pinned layer, a free layer above the spacer layer, a heating device, for heating the free layer to induce a paramagnetic thermal instability in the free layer whereby a magnetization of the free layer randomly switches between different detectable magnetic states upon heating thereof, and a magnetoresistance detection circuit for detecting an instantaneous magnetic state of the free layer.”

The patent application was filed on September 28, 2018 (16/147,516).

Storage system having adaptive workload-based command processing clock
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,534,546) developed by Benisty, Shay, Beer-Shava, Israel, and Sharifie, Tal, Lehavim, Israel, for a “storage system having an adaptive workload-based command processing clock.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A storage system having an adaptive workload-based command processing clock is provided. In one embodiment, a storage system has a memory, a command processing path, and a controller in communication with the memory and the command processing path. The controller is configured to adapt an input clock signal based on a current workload of the controller and provide the adapted clock signal to the command processing path in the controller.”

The patent application was filed on June 13, 2017 (15/621,480).

Non-binary encoding for non-volatile memory
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,530,391) developed by Galbraith, Richard Leo, Rochester, MN, Goode, Jonas Andrew, Lake Forest, CA, and Ravindran, Niranjay, Rochester, MN, for a “non-binary encoding for non-volatile memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data storage system and method are provided for storing data in non-volatile memory devices. Binary data is received for storage in a non-volatile memory device. The binary data is converted into non-binary data comprising base-X values, where X is an integer greater than two. The non-binary data is encoded to generate a codeword and the codeword is written to a wordline of the non-volatile memory device.”

The patent application was filed on July 27, 2017 (15/662,158).

Data storage device employing memory processing of un-converged codewords
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,530,390) developed by Oboukhov, Iouri, Hanson, Weldon M., Ravindran, Niranjay, and Galbraith, Richard L., Rochester, MN, for a “data storage device employing memory efficient processing of un-converged codewords.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data storage device is disclosed comprising a head actuated over a disk comprising a data track having at least a first data segment and a second data segment. A first plurality of codewords are generated, and a first parity sector is generated over the first plurality of codewords. The first plurality of codewords and the first parity sector are written to the first data segment. A second plurality of codewords are generated, and a second parity sector is generated over the second plurality of codewords. The second plurality of codewords and the second parity sector are written to the second data segment. During a read operation the data segments of the data track are processed sequentially to decode the codewords using a low density parity check, (LDPC) decoder, wherein the reliability metrics of un-converged codewords are stored in a codeword buffer and updated using the respective parity sector.”

The patent application was filed on May 17, 2018 (15/983,033).

Uniform performance monitor for data storage device and method of operation
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,528,506) developed by Hodes, Avichay Haim, Kfar Ben Nun, Israel, and Hahn, Judah Gamliel, Ofra, Israel, for an “Uniform performance monitor for a data storage device and method of operation.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”An apparatus includes a first interface configured to receive a first message from a host device or from a data storage device. The apparatus further includes a buffer and a second interface. The buffer is coupled to the first interface and is configured to store the first message. The second interface is coupled to the buffer and is configured to provide the first message to the data storage device or to the host device, respectively. The second interface is further configured to provide, at a time based on a performance metric associated with the first message, a second message to the data storage device or to the host device, respectively. The apparatus further includes a circuit configured to determine the performance metric.”

The patent application was filed on October 18, 2017 (15/786,763).

Recovering from corruptions in data processing units in non-volatile memory
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,528,426) developed by Dubeyko, Viacheslav Anatolyevich, and Cargnini, Luis Vitorio, San Jose, CA, for “methods, systems and devices for recovering from corruptions in data processing units in non-volatile memory devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Systems and methods are disclosed for recovering from various types of data and process corruptions at a data processing unit of a plurality of data processing units each coupled with a non-volatile memory divided into a plurality of selectable locations, in a system absent a central processing unit. In some embodiments a data processing unit is configured to determine validity of an allocation table of the data processing unit, retrieve a process descriptor from the allocation table, parse the non-volatile memory for a first set of process data corresponding to the process descriptor, determine validity of the first set of process data corresponding to the process descriptor and attempt to recover the first set of process data in accordance with a determination that the first set of process data is invalid.”

The patent application was filed on November 30, 2017 (15/828,104).

Advanced flash scan algorithm
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,528,269) developed by Elliott, Mark, San Diego, CA, for an “advanced flash scan algorithm.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A controller of a storage system may poll a non-volatile memory component to determine an operational status of the memory component after a memory operation has been initiated in the memory component. The controller may, in response to determining the operational status of the memory component is busy, update a polling interval based on a polling factor. The controller may re-poll the memory component to determine the operational status of the memory component after expiration of the updated polling interval. The controller may repeat the updating of the polling interval and the re-polling of the memory component until the operational status of the memory component is determined to be ready or until a predetermined number of iterations of the updating and re-polling have been performed if, in response to the re-polling, the operational status is determined to be busy.”

The patent application was filed on April 23, 2018 (15/959,773).

Write latency reduction
Western Digital Technologies, Inc., Irvine, CA, has been assigned a patent (10,528,265) developed by Malina, James N., Irvine, CA, Anderson, Kent, Broomfield, CO, and Alexander, James C., Newport Coast, CA, for a “write latency reduction.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data storage system includes a plurality of Data Storage Devices, (DSDs). A write command is sent to each DSD of the plurality of DSDs to each store one or more erasure coded shards of an overprovisioned number of shards. The overprovisioned number of shards is generated from an erasure coding on data to provide at least a predetermined level of data reliability. Write complete indications are received for a threshold number of shards less than the overprovisioned number of shards, with each write complete indication indicating that one or more shards of the overprovisioned number of shards has been stored in a DSD. It is determined that the data has been written with at least the predetermined level of data reliability after receiving write complete indications for the threshold number of shards, but before receiving write complete indications for all of the overprovisioned number of shards.”

The patent application was filed on September 3, 2016 (15/256,522).

Thermal aware workload scheduling
Western Digital Technologies, Inc., Irvine, CA, has been assigned a patent (10,528,098) developed by Amin-Shahidi, Darya, Dhanda, Abhishek, and Hirano, Toshiki, San Jose, CA, for a “thermal aware workload scheduling.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Systems, software, devices, and methods of distributing a workload among available data storage devices in a thermal aware manner are described herein. More specifically, the examples herein discuss distributing the workload among the available data storage devices in a thermal aware manner that optimizes collective IOPs of the data storage devices in an enclosure. The thermal aware distribution of the storage operations is determined by a thermal model that predicts thermal characteristics of the data storage system based on inlet air characteristics of the enclosure, performance characteristics and thermal constraints of the data storage devices, and constraints of the workload.”

The patent application was filed on June 29, 2016 (15/197,410).

Data storage device sorting execution order of commands based on predicted future command
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,522,185) developed by Hall, David R., Rochester, MN, for a “data storage device sorting execution order of commands based on a predicted future command.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data storage device is disclosed comprising a head actuated over a disk. A plurality of access commands are stored in a command queue, wherein the access commands are for accessing the disk using the head. A future access command is predicted, and an execution order for the access commands in the command queue is determined based on an associated execution cost of at least some of the access commands in the command queue and an associated execution cost of the future access command. At least one of the access commands in the command queue is executed based on the execution order.”

The patent application was filed on February 9, 2019 (16/271,793).

HAMR read/write head with reversed read head and write head
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,522,176) developed by Yan, Wentao, and Knutson, Neil David, Fremont, CA, for a “heat-assisted magnetic recording, (HAMR) read/write head with reversed read head and write head.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A heat-assisted magnetic recording, (HAMR) disk drive read/write head has the write head located adjacent the trailing surface of the gas-bearing slider with the read head located adjacent the write head, which is the reversed location from conventional read/write heads. This results in reduced write head protrusion during writing which allows for a reduced minimum fly-height for the slider. For a HAMR read/write head that uses a heater to protrude the read head closer to the disk during reading, the reversed location allows for better heater efficiency and thus reduced heater power.”

The patent application was filed on February 15, 2019 (16/276,734).

Non-volatile memory device with secure read
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,521,617) developed by Sela, Rotem, Hod Hasharon, Israel, and Levi, Enosh, Kochav Yair, Israel, for a “non-volatile memory device with secure read.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Technology that provides security for a requestor of data stored in a non-volatile memory device is disclosed. In one aspect, the non-volatile memory device provides data on a host interface only if a digest for the data matches an expected digest for the data. The non-volatile memory device may store expected digests for data for various logical addresses. Upon receiving a request on the host interface to read data for a logical address, the non-volatile memory device may access the data for the logical address, compute a digest for the accessed data, and compare the computed digest with the expected digest. The non-volatile memory device provides the accessed data on the host interface only if the computed digest matches the expected digest, in one aspect. The non-volatile memory device may be used to provide a secure boot of a host.”

The patent application was filed on August 14, 2017 (15/676,708).